WM8711BL Wolfson Microelectronics, WM8711BL Datasheet - Page 21

• Manufacturer Part Number: WM8711BL
• Description: Ultra-Small Audio DAC
• Manufacturer: Wolfson Microelectronics

Production Data
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CLOCKOUT
The Core Clock is internally buffered and made available externally to the audio system on the
CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for
driving external loads.
There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will
inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to
Electrical Characteristics.
CLKOUT can also be divided by 2 under software control, refer to Table 7. Note that if CLKOUT is not
required then the CLKOUT buffer on the WM8711BL can be safely powered down to conserve power
(see POWER DOWN section). If the system architect has the choice between using F
or F
by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical
Characteristics for timing information.
Table 7 Programming CLKOUT
CLKOUT is disabled and set low whenever the device is in reset.
DIGITAL AUDIO INTERFACES
WM8711BL may be operated in either one of the 4 offered audio interface modes. These are:
•
•
•
•
All four of these modes are MSB first and operate with data 16 to 32 bits, except in right justified
mode where 32 bit data is not supported.
The digital audio interface receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether
Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous with the
BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always an input.
BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section
0001000
Sampling
Control
REGISTER
ADDRESS
CLKOUT
Right justified
Left justified
I
DSP mode
2
S
= F
MCLK
/2 in the interface, the latter is recommended to conserve power. When the divide
7
BIT
CLKODIV2
LABEL
0
DEFAULT
CLKOUT divider select
1 = CLOCKOUT is Core Clock
0 = CLOCKOUT is Core Clock
divided by 2
DESCRIPTION
PD, Rev 4.1, April 2007
WM8711BL
CLKOUT
= F
MCLK
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