WM8711BL Wolfson Microelectronics, WM8711BL Datasheet - Page 10

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WM8711BL

Manufacturer Part Number
WM8711BL
Description
Ultra-Small Audio DAC
Manufacturer
Wolfson Microelectronics
Datasheet
WM8711BL
Figure 1 System Clock Timing Requirements
Figure 2 Digital Audio Data Timing - Master Mode
w
MASTER CLOCK TIMING
DIGITAL AUDIO INTERFACE – MASTER MODE
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T
CLKDIV2=0 unless otherwise stated.
System Clock Timing Information
MCLK System clock pulse width
high
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T
256fs unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
DACLRC propagation delay
from BCLK falling edge
DACDAT setup time to
BCLCK rising edge
DACDAT hold time from
BCLK rising edge
PARAMETER
MCLK
SYMBOL
t
t
t
DHT
DST
SYMBOL
DL
t
t
t
XTIH
XTIL
XTIY
t
XTIL
t
XTIY
TEST CONDITIONS
TEST CONDITIONS
t
XTIH
A
A
= +25
= +25
o
40:60
C, Slave Mode fs = 48kHz, MCLK = 256fs
MIN
MIN
o
18
18
54
10
10
C, Slave Mode, fs = 48kHz, XTI/MCLK =
0
TYP
TYP
PD, Rev 4.1, April 2007
60:40
MAX
MAX
10
Production Data
UNIT
UNIT
ns
ns
ns
ns
ns
ns
10

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