nRF24E2 Nordic VLSI, nRF24E2 Datasheet - Page 68

• Manufacturer Part Number: nRF24E2
• Description: Single Chip RF Transmitter + MCU + ADC NRF2402 2.4GHz RF Transmitter
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
TH0 functions as an independent 8-bit counter. However, TH0 can count only CPU
clock cycles (divided by 4 or by 12). The Timer 1 control and flag bits (TR1 and TF1)
are used as the control and flag bits for TH0.
When Timer 0 is in mode 3, Timer 1 has limited usage because Timer 0 uses the
Timer 1 control bit (TR1) and interrupt flag (TF1). Timer 1 can still be used for baud
rate generation and the Timer 1 count values are still available in the TL1 and TH1
registers.Control of Timer 1 when Timer 0 is in mode 3 is through the Timer 1 mode
bits. To turn Timer 1 on, set Timer 1 to mode 0, 1, or 2. To turn Timer 1 off, set it to
mode 3. The Timer 1 C/T bit and T1M bit are still available to Timer 1. Therefore,
Timer 1 can count CPU_clk/4, CPU_clk/12, or high-to-low transitions on the t1 pin.
The Timer 1 GATE function is also available when Timer 0 is in mode 3.
The default timer clock scheme for the nRF24E2 timers is twelve CPU clock cycles
per increment, the same as in the standard 8051. However, in the nRF24E2, the
instruction cycle is four clock cycles.
Using the default rate (twelve clocks per timer increment) allows existing application
code with real-time dependencies, such as baud rate, to operate properly. However,
applications that require fast timing can set the timers to increment every four clock
cycles by setting bits in the Clock Control register (CKCON) at SFR location 0x8E,
described in Table 10-15 : CKCON Register – SFR 0x.
The CKCON bits that control the timer clock rates are:
When a CKCON register bit is set to 1, the associated counter increments at four-
clock intervals. When a CKCON bit is cleared, the associated counter increments at
twelve-clock intervals. The timer controls are independent of each other. The default
setting for all three timers is 0; that is, twelve-clock intervals. These bits have no
effect in counter mode.
Bit
CKCON.7,6
CKCON.5
CKCON.4
CKCON.3
CKCON.2–0
Table 10-15 : CKCON Register – SFR 0x8E,
default initial data value is 0x01, i.e. MOVX takes 3 cycles.
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Revision: 1.0
CKCON bit Counter/Timer
5
4
3
Timer 2
Timer 1
Timer 0
compatibility with 80C32); when T2M = 1, Timer 2 uses CPU_clk/4. This bit has
no effect when Timer 2 is configured for baud rate generation.
compatibility with 80C32); when T1M = 1, Timer 1 uses CPU_clk/4.
compatibility with 80C32); when T0M = 1, Timer 0 uses CPU_clk/4.
instructions; number of cycles is 2 + { MD2, MD1, MD0}
Function
Reserved
T2M – Timer 2 clock select. When T2M = 0, Timer 2 uses CPU_clk/12 (for
MD2, MD1, MD0 – Control the number of cycles to be used for external MOVX
T1M – Timer 1 clock select. When T1M = 0, Timer 1 uses CPU_clk/12 (for
T0M – Timer 0 clock select. When T0M = 0, Timer 0 uses CPU_clk/12 (for
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August 2003