nRF24E2 Nordic VLSI, nRF24E2 Datasheet - Page 65

• Manufacturer Part Number: nRF24E2
• Description: Single Chip RF Transmitter + MCU + ADC NRF2402 2.4GHz RF Transmitter
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
Table 10-13 : TMOD Register – SFR 0x89
Bit
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
Table 10-14 : TCON Register – SFR 0x88
10.8.1.1 Mode 0
Mode 0 operation, illustrated in Figure 10-2 : Timer 0/1 – Modes 0 and 1, is the same
for Timer 0 and Timer 1. In mode 0, the timer is configured as a 13-bit counter that
uses bits 0–4 of TL0 (or TL1) and all eight bits of TH0 (or TH1). The timer enable bit
(TR0/TR1) in the TCON SFR starts the timer. The C/T bit selects the timer/counter
clock source, CPU_clk or t0/t1. The timer counts transitions from the selected source
as long as the GATE bit is 0, or the GATE bit is 1 and the corresponding interrupt pin
(INT0_N or INT1_N) is deasserted. INT0_N and INT1_N are alternate function bits
of Port0, please seeTable 3-1 : Port functions. When the 13-bit count increments from
0x1FFF (all ones), the counter rolls over to all zeros, the TF0 (or TF1) bit is set in the
TCON SFR, and the t0_out (or t1_out) pin goes high for one clock cycle. The upper
three bits of TL0 (or TL1) are indeterminate in mode 0 and must be masked when the
software evaluates the register.
10.8.1.2 Mode 1
Mode 1 operation is the same for Timer 0 and Timer 1. In mode 1, the timer is
configured as a 16-bit counter. As illustrated in Figure 10-2 : Timer 0/1 – Modes 0
and 1, all eight bits of the LSB register (TL0 or TL1) are used. The counter rolls over
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Revision: 1.0
Function
TF1 - Timer 1 overflow flag. Set to 1 when the Timer 1 count overflows and cleared when
the CPU vectors to the interrupt service routine.
TR1 - Timer 1 run control. Set to 1 to enable counting on Timer 1.
TF0 - Timer 0 overflow flag. Set to 1 when the Timer 0 count overflows and cleared when
the CPU vectors to the interrupt service routine.
TR0 - Timer 0 run control. Set to 1 to enable counting on Timer 0.
IE1 - Interrupt 1 edge detect. If external interrupt 1 is configured to be edge-sensitive (IT1
= 1), IE1 is set by hardware when a negative edge is detected on the INT1_N external
interrupt pin and is automatically cleared when the CPU vectors to the corresponding
interrupt service routine. In edge-sensitive mode, IE1 can also be cleared by software.
If external interrupt 1 is configured to be level-sensitive (IT1 = 0), IE1 is set when the
INT1_N pin is low and cleared when the INT1_N pin is high. In level-sensitive mode,
software cannot write to IE1.
IT1 - Interrupt 1 type select. When IT1 = 1, the nRF24E2 detects external interrupt pin
INT1_N on the falling edge (edge-sensitive). When IT1 = 0, the nRF24E2 detects INT1_N
as a low level (level-sensitive).
IE0 - Interrupt 0 edge detect. If external interrupt 0 is configured to be edge-sensitive (IT0
= 1), IE0 is set by hardware when a negative edge is detected on the INT0_N external
interrupt pin and is automatically cleared when the CPU vectors to the corresponding
interrupt service routine. In edge-sensitive mode, IE0 can also be cleared by software.
If external interrupt 0 is configured to be level-sensitive (IT0 = 0), IE0 is set when the
INT0_N pin is low and cleared when the INT0_N pin is high. In level-sensitive mode,
software cannot write to IE0.
IT0 - Interrupt 0 type select. When IT1 = 1, the nRF24E2 detects external interrupt
INT0_N on the falling edge (edge-sensitive). When IT1 = 0, the nRF24E2 detects INT0_N
as a low level (level-sensitive).
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August 2003