nRF24E2 Nordic VLSI, nRF24E2 Datasheet - Page 36

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nRF24E2

Manufacturer Part Number
nRF24E2
Description
Single Chip RF Transmitter + MCU + ADC NRF2402 2.4GHz RF Transmitter
Manufacturer
Nordic VLSI
Datasheet

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PRODUCT SPECIFICATION
Figure 5-3 : Timing diagram single step conversion.
ADCRUN=0, and conversion is started at first posedge ADCCLK after CSTARTN
has gone high. A pulse is generated on ADC_EOF when the converted value is
available on the ADCDATA bus. Conversion time t
t
bit conversion is shown. Minimum width of a CSTARTN pulse is 1 clock cycle. If a
new CSTARTN pulse comes before previous conversion has finished, the previous
conversion will be aborted.
Figure 5-4 : Timing diagram continuous mode conversion.
ADCRUN=1, and CSTARTN is ignored. Cycle time t
conversion. t
figure is showing 10 bit conversions.
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
Conv
= N/2 + 3 clock cycles, where N is number of resolution bits. In the figure a 10
input signal
ADCCLK
ADCCLK
ADC_EOC
ADCDATA
CSTARTN
ADC_EOC
ADCDATA
sample
Cycle
= N/2 +1 clock cycles, where N is number of resolution bits. The
n
any previously converted value is held until
input signal
sampled
QhtrÃ"%ÂsÃ(
t
Conv
new ADC_EOC
sample n-1
t
Cycle
Conv
t
Cycle
Conv
n+1
depends on resolution,
is the time between each
sample n
August 2003
n+2

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