LPC2292 Philips Semiconductors (Acquired by NXP), LPC2292 Datasheet - Page 21

• Manufacturer Part Number: LPC2292
• Description: 16/32-bit Arm Microcontrollers; 256 KB Isp/iap Flash With CAN, 10-bit ADC And External Memory Interfacebased on a 16/32 Bit ARM7TDMI-STM Cpu With Real-time Emulation And Embedded Trace Support, Together With 256 Kilobytes (kB) of Embedded High Speed
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
9397 750 12748
Preliminary data
6.14.1 Features
6.15.1 Features
6.14 UARTs
6.15 I
6.16 SPI serial I/O controller
The LPC2292/LPC2294 each contain two UARTs. One UART provides a full modem
control handshake interface, the other provides only transmit and receive data lines.
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(SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter
with the capability to both receive and send information (such as memory).
Transmitters and/or receivers can operate in either master or slave mode, depending
on whether the chip has to initiate a data transfer or is only addressed. I
multi-master bus, it can be controlled by more than one bus master connected to it.
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The LPC2292/LPC2294 each contain two SPIs. The SPI is a full duplex serial
interface, designed to be able to handle multiple masters and slaves connected to a
given bus. Only a single master and a single slave can communicate on the interface
during a given data transfer. During a data transfer the master always sends a byte of
data to the slave, and the slave always sends a byte of data to the master.
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C is a bi-directional bus for inter-IC control using only two wires: a serial clock line
C implemented in LPC2292/LPC2294 supports bit rate up to 400 kbit/s (Fast I
C serial I/O controller
16 byte Receive and Transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in baud rate generator.
Standard modem interface signals included on UART1.
Standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
The I
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C bus may be used for test and diagnostic purposes.
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C compliant bus interface.
Rev. 01 — 05 February 2004
16/32-bit ARM microcontrollers with external memory interface
LPC2292/LPC2294
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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