AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 291

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

SAMPLE_PRELOAD (0x2)
AVR_RESET (0xC)
BYPASS (0xF)
Boundary-scan Related
Register in I/O Memory
MCU Control Register –
MCUCR
MCU Status Register –
MCUSR
4250C–CAN–03/04
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of
the input/output pins without affecting the system operation. However, the output latches
are not connected to the pins. The Boundary-scan Chain is selected as data register.
The active states are:
•
•
•
The AVR specific public JTAG instruction for forcing the AVR device into the Reset
mode or releasing the JTAG reset source. The TAP controller is not reset by this instruc-
tion. The one bit Reset Register is selected as data register.
Note that the reset will be active as long as there is a logic “one” in the Reset Chain.
The output from this chain is not latched.
The active states are:
•
Mandatory JTAG instruction selecting the Bypass Register for data register.
The active states are:
•
•
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.
If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling
or enabling of the JTAG interface, a timed sequence must be followed when changing
this bit: The application software must write this bit to the desired value twice within four
cycles to change its value. Note that this bit must not be altered when using the On-chip
Debug system.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be
set to one. The reason for this is to avoid static current at the TDO pin in the JTAG
interface.
The MCU Status Register provides information on which reset source caused an MCU
reset.
Bit
Read/Write
Initial Value
Bit
Read/Write
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
Update-DR: Data from the Boundary-scan chain is applied to the output latches.
However, the output latches are not connected to the pins.
Shift-DR: The Reset Register is shifted by the TCK input.
Capture-DR: Loads a logic “0” into the Bypass Register.
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
JTD
R/W
R
7
0
7
–
R
R
6
–
0
6
–
R
R
5
–
0
5
–
JTRF
PUD
R/W
R/W
4
0
4
WDRF
R/W
R
3
–
0
3
BORF
R/W
R
2
–
0
2
AT90CAN128
EXTRF
IVSEL
R/W
R/W
1
0
1
PORF
IVCE
R/W
R/W
0
0
0
MCUCR
MCUSR
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