AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 136

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Timer/Counter3 Control
Register C – TCCR3C
Timer/Counter1 – TCNT1H and
TCNT1L
Timer/Counter3 – TCNT3H and
TCNT3L
136
AT90CAN128
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a
non-PWM mode. However, for ensuring compatibility with future devices, these bits
must be set to zero when TCCRnA is written when operating in a PWM mode. When
writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare match is
forced on the Waveform Generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are
implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that
determine the effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer
in Clear Timer on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnC bits are always read as zero.
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit tempo-
rary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 112
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing
a compare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following
timer clock for all compare units.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
FOC3A
R/W
R/W
R/W
7
0
7
0
7
0
FOC3B
R/W
R/W
R/W
6
0
6
0
6
0
FOC3C
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
TCNT1[15:8]
TCNT3[15:8]
R
4
0
4
0
4
–
0
TCNT1[7:0]
TCNT3[7:0]
R/W
R/W
3
0
3
0
R
3
–
0
R/W
R/W
2
0
2
0
2
–
R
0
R/W
R/W
1
0
1
0
R
1
–
0
R/W
R/W
0
0
0
0
0
–
R
0
4250C–CAN–03/04
TCNT1H
TCNT3H
TCNT1L
TCNT3L
TCCR3C