AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 168

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

168
AT90CAN128
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 78 and Figure 79 for an example. The CPOL func-
tionality is summarized below:
Table 72. CPOL Functionality
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 78 and Figure 79 for an example.
The CPOL functionality is summarized below:
Table 73. CPHA Functionality
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the clk
quency f
Table 74. Relationship Between SCK and the Oscillator Frequency
SPI2X
0
0
0
0
1
1
1
1
clkio
CPOL
CPHA
is shown in the following table:
0
1
0
1
SPR1
0
0
1
1
0
0
1
1
Leading Edge
Leading Edge
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
f
f
f
f
f
f
f
f
clkio
clkio
clkio
clkio
clkio
clkio
clkio
clkio
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
4250C–CAN–03/04
IO
fre-