HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 47

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
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Name
MST_MODE1
MST_MODE2
F0_CNT_L
F0_CNT_H
C/I
Addr.
15h
16h
18h
19h
28h
Bits
3..2
5..4
3..2
5..4
7..6
7..0
7..0
3..0
7..4
0
1
6
7
0
1
r/w Function
r/w on read: indication
w
w
w
w
w
w
w
w
w
w
w
r
r
'0' disable AUX1 channel data mirroring (reset default)
'1' mirror AUX1 receive to AUX1 transmit
enable/disable AUX2 channel mirroring
'0' disable AUX2 channel data mirroring (reset default)
'1' mirror AUX2 receive to AUX2 transmit
'00'
'01'
'10'
'11'
'00'
'01'
'10'
'11'
MST test loop
When set MST output data is looped to the MST inputs.
enable PCM/GCI/IOM2 write slots
'0' disable PCM/GCI/IOM2 write slots; slot #2 and slot #3
'1' enables slot #2 and slot #3 as master, D- and C/I-channel
(see also Timing diagram 5: PCM/GCI/IOM2 timing on page
59)
'1' generate frame signal for OKI
(see also Timing diagram 5: PCM/GCI/IOM2 timing on page
59)
'00'
'01'
'10'
'11'
16 bit 125µs time counter (low byte)
16 bit 125µs time counter (high byte)
on write: command
enable/disable AUX1 channel mirroring
DPLL adjust speed
PCM data rate
'1' generate frame signal for OKI
unused, must be '0'
PCM/GCI/IOM2 slot select for higher data rates
unused, must be '0'
F0IO pulse count
F0IO pulse count
unused
may be used for normal data
C4IO clock is adjusted in the last time slot of MST
frame 4 times by one half clock cycle
C4IO clock is adjusted in the last time slot of MST
frame 3 times by one half clock cycle
C4IO clock is adjusted in the last time slot of MST
frame twice by one half clock cycle
C4IO clock is adjusted in the last time slot of MST
frame once by one half clock cycle
slots 31..0 accessable
slots 63..32 accessable
slots 95..64 accessable
slots 127..96 accessable
2MBit/s (PCM30)
4MBit/s (PCM64)
8MBit/s (PCM128)
unused
TM
TM
CODECs on F1_A
CODECs on F1_B
Cologne
Chip
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