HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 4

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
4.2
4.3
4.4
4.5
5
6
6.1
6.2
6.3
6.4
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
8.1
8.2
9
9.1
9.2
10
10.1
10.2
11
12
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6.1.1
6.1.2
6.2.1
6.2.2
6.3.1
6.3.2
7.1.1
7.1.2
7.1.3
7.2.1
7.2.2
Electrical characteristics ................................................................................................................. 53
Timing characteristics ..................................................................................................................... 55
External circuitries........................................................................................................................... 63
State matrices for NT and TE ......................................................................................................... 73
Binary organisation of the frames .................................................................................................. 75
Clock synchronisation...................................................................................................................... 77
HFC-S USB package dimensions.................................................................................................... 79
ISDN USB TA sample circuitry with HFC-S USB........................................................................ 80
FIFO, interrupt, status and control registers .................................................................................. 36
Auxiliary port registers .................................................................................................................. 44
PCM/GCI/IOM2 bus section registers........................................................................................... 45
S/T section registers....................................................................................................................... 49
Microprocessor access ................................................................................................................... 55
Auxiliary port access ..................................................................................................................... 57
PCM/GCI/IOM2 timing................................................................................................................. 59
EEPROM access ............................................................................................................................ 62
S/T interface circuitry.................................................................................................................... 63
Oscillator circuitry for USB clock................................................................................................. 68
Oscillator circuitry for S/T clock................................................................................................... 69
EEPROM circuitry......................................................................................................................... 70
Auxiliary port circuitry .................................................................................................................. 71
Power supply from USB ................................................................................................................ 72
USB connection ............................................................................................................................. 72
S/T interface activation/deactivation layer 1 for finite state matrix for NT .................................. 73
Activation/deactivation layer 1 for finite state matrix for TE ....................................................... 74
S/T frame structure ........................................................................................................................ 75
GCI frame structure ....................................................................................................................... 76
Clock synchronisation in NT-mode........................................................................................... 77
Clock synchronisation in TE-mode ........................................................................................... 78
Register write access ............................................................................................................. 55
Register read access .............................................................................................................. 56
Auxiliary port write access ................................................................................................... 57
Auxiliary port read access..................................................................................................... 58
Master mode.......................................................................................................................... 60
Slave mode ............................................................................................................................ 61
External receiver circuitry..................................................................................................... 63
External wake-up circuitry.................................................................................................... 64
External transmitter circuitry ................................................................................................ 65
Oscillator circuitry with coil ................................................................................................. 68
Oscillator circuitry without coil ............................................................................................ 68
Cologne
Chip
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