HFC-SUSB Cologne Chip AG, HFC-SUSB Datasheet - Page 45

• Manufacturer Part Number: HFC-SUSB
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C EC2
4.4
Timeslots for transmit direction
Timeslots for receive direction
Data registers
*)
:e\i " !
Name
B1_SSL
B2_SSL
AUX1_SSL
AUX2_SSL
Name
B1_RSL
B2_RSL
AUX1_RSL
AUX2_RSL
Name
B1_D
B2_D
AUX1_D
AUX2_D
*
Enabling more than one channel on the same slot causes undefined output data.
These registers are read/written automatically by the HDLC FIFO controller (HFC) or PCM controller
and need not be accessed by the user. To read/write data the FIFO registers should be used.
important!
*)
*)
PCM/GCI/IOM2 bus section registers
*)
*)
Addr.
Addr.
Addr.
2Ch
2Dh
2Eh
2Fh
20h
21h
22h
23h
24h
25h
26h
27h
Bits
Bits
Bits
4..0
4..0
0..7
5
6
7
5
6
7
r/w Function
r/w Function
r/w Function
r/w read/write data registers for selected timeslot data
w
w
w
w
w
w
w
w
64..95, 96..127, see MST_MODE2 register bits 5..4)
select PCM/GCI/IOM2 bus data lines
'0' STIO1 output
'1' STIO2 output
transmit channel enable for PCM/GCI/IOM2 bus
'0' disable (reset default)
'1' enable
96..127, see MST_MODE2 register bits 5..4)
select PCM/GCI/IOM2 bus data lines
'0' STIO2 is input
'1' STIO1 is input
receive channel enable for PCM/GCI/IOM2 bus
'0' disable (reset default)
'1' enable
select PCM/GCI/IOM2 bus transmission slot (0..31, 32..63,
unused
select PCM/GCI/IOM2 bus receive slot (0..31, 32..63, 64..95,
unused
Cologne
Chip
$% _V ("