AD9927 Analog Devices, AD9927 Datasheet - Page 86

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

AD9927
Address
15
16
17
18
19
1A
1B
1C
1D
1F
Table 50. VD/HD Registers
Address
20
21
22
Table 51. I/O and Charge Pump Registers
Address
23
Data Bits
[0]
[0]
[12:0]
[25:13]
Data
Bits
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[9:7]
Data
Bits
[0]
[27:0]
[12:0]
[13]
[14]
[15]
[16]
[27:0]
[27:0]
[27:0]
[27:0]
[23:0]
[23:0]
[24]
[0]
[1]
Default
Value
0
0
0
0
0
0
0
1
Default
Value
0
0
0
0
0
0
0
0
0
0
A
FF0000
0
0
1
1
Default Value
0
0
0
0
SCK
Update
Type
Update
Type
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
VD
VD
Update Type
Name
OSC_NVR
XV_NVR
IO_NVR
DATA_NVR
TEST
TEST
LDO_32_EN
HCLKMODE
Name
OSC_RSTB
TEST
UPDATE
PREVENTUP
SYNC_RST_SHUTEN
REG_RST_SHUT
GPO_RST_SYNC
TEST
TEST
TEST
TEST
VSGSELECT
VSGMASK_CTL
VSGMASK_CTL_EN
HCNT14_EN
PBLK_MASK_EN
Rev. 0 | Page 86 of 100
MASTER
VDHDPOL
HDRISE
VDRISE
Name
Test use only. Set to 0.
Test use only. Set to 0.
1: internal regulator enable for 3.2 V output.
Description
Oscillator normal voltage range. Set to match CLIVDD supply voltage.
0 = 1.8 V, 1 = 3.3 V
XV output normal voltage range. Set to match XVVDD supply voltage.
0 = 1.8 V, 1 = 3.3 V
I/O normal voltage range. Set the match IOVDD supply voltage.
0 = 1.8 V, 1 = 3.3 V
Data pin normal voltage range. Set to match DRVDD supply voltage.
0 = 1.8 V I/O, 1 = 3.3 V I/O.
Selects HCLK output configuration. Should be written to desired value.
001 = Mode 1, 010 = Mode 2, 100 = Mode 3. All other values are invalid.
Description
VD/HD master or slave mode. 0: slave mode; 1: master mode.
VD/HD active polarity. 0 = low, 1 = high.
Rising edge location for HD. Minimum value is 36 pixels.
Rising edge location for VD.
Test mode only. Must be set to 0.
1: forces shutter control to reset.
1: reset shutter and GPO control at SYNC operation.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0xA.
Each bit selects XV pulses for use as VSG pulses.
Description
CLO oscillator reset bar.
0: oscillator in power-down state; 1: resume oscillator
operation.
Serial update line.
Sets the line (HD) within the field to update the VD-updated
registers.
Prevents the update of the VD-updated registers.
0: normal update; 1: prevent update of VD-updated registers.
1: enable reset of the shutter control after SYNC operation
occurs.
VSG masking. Overrides settings in field registers when
enabled.
0: disable VSGMAK_CTL bits. VSG masking is controlled by field
registers.
1: enable VSGMASK_CTL bits to control VSG masking
1: enable 14-bit H-counter.
1: disable clamp operation if PBLK is active at the same time as
CLPOB.