AD9927 Analog Devices, AD9927 Datasheet - Page 82

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

AD9927
SERIAL INTERFACE TIMING
The internal registers of the AD9927 are accessed through a
3-wire serial interface. Each register consists of a 12-bit address
and a 28-bit data-word. Both the 12-bit address and 28-bit data-
word are written starting with the LSB. To write to each register,
a 40-bit operation is required, as shown in Figure 97. Although
many registers are fewer than 28 bits wide, all 28 bits must be
written for each register. For example, if the register is only 20 bits
wide, the upper eight bits are don’t cares and must be filled with
0s during the serial write operation. If fewer than 28 data bits are
written, the register is not updated with new data.
SDATA
SCK
SL
SDATA
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 28-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 28-BIT DATA-WORD (ALL 28 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
SCK
SL
A0
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 40 BITS MUST BE WRITTEN: 12 BITS FOR ADDRESS AND 28 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <28 BITS, 0s MUST BE USED TO COMPLETE THE 28-BIT DATA LENGTH.
4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE
1
PARTICULAR REGISTER WRITTEN TO. SEE THE UPDATING OF NEW REGISTER VALUES SECTION FOR MORE INFORMATION.
A0
A1
1
2
A1
A2
t
LS
2
3
A2
A3
3
4
A3
4
A4
5
t
DS
A10 A11
A5
11
6
Figure 98. Continuous Serial Write Operation
12-BIT ADDRESS
A6
12
7
A7
Figure 97. Serial Write Operation
D0
13
8
DATA FOR STARTING
t
REGISTER ADDRESS
Rev. 0 | Page 82 of 100
A8
D1
DH
14
9
A9
10
A10
11
D26
A11
Figure 98 shows a more efficient way to write to the registers,
using the AD9927’s address autoincrement capability. Using this
method, the lowest desired address is written first, followed by
multiple 28-bit data-words. Each new 28-bit data-word is
automatically written to the next highest register address. By
eliminating the need to write each 12-bit address, faster register
loading is achieved. Continuous write operations can be used
starting with any register location.
12
39
D27
D0
13
40
D0
D1
14
41
REGISTER ADDRESS
D2
D1
15
DATA FOR NEXT
42
D3
28-BIT DATA
16
D26
67
D25
D27
38
68
D26
t
D0
LH
69
39
D27
D1
70
40
D2
71