AD9927 Analog Devices, AD9927 Datasheet - Page 6

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

AD9927
TIMING SPECIFICATIONS
C
Table 4.
Parameter
MASTER CLOCK (See Figure 16)
VD FALLING EDGE TO HD FALLING EDGE IN SLAVE MODE (See Figure 89)
AFE CLPOB PULSE WIDTH (See Figure 23 and Figure 33)
AFE SAMPLE LOCATION (See Figure 17 and Figure 20)
DATA OUTPUTS (See Figure 21 and Figure 22)
SERIAL INTERFACE (See Figure 97)
1
2
Parameter is programmable.
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
L
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal Pixel Position 0
SHP Sample Edge to SHD Sample Edge
Output Delay from DCLK Rising Edge
Inhibited Area for DOUTPHASE Edge Location
Pipeline Delay from SHP/SHD Sampling to DOUT
Maximum SCK Frequency (Must Not Exceed CLI Frequency)
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
= 20 pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3.0 V, f
1
1, 2
Rev. 0 | Page 6 of 100
CLI
= 40 MHz, unless otherwise noted.
Symbol
t
t
t
t
t
t
f
t
t
t
t
SCLK
CONV
CLIDLY
VDHD
S1
OD
DOUTINH
LS
LH
DS
DH
Min
25
10
0
2
11
SHDLOC + 1
40
10
10
10
10
Typ
12.5
6
20
12.5
1
16
Max
15
VD period − 5 × t
SHDLOC + 15
CONV
Unit
ns
ns
ns
ns
Pixels
ns
ns
Edge
location
Cycles
MHz
ns
ns
ns
ns