AD9927 Analog Devices, AD9927 Datasheet - Page 67

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

XV1 TO XV24
SYNC
H1 TO H4, RG,
SCP
DESIGNATOR
XV1 TO XV24
VSG, SUBCK
HD
VD
SYNC
FIELD
NOTES
1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13).
4. THE SYNC RISING EDGE CAUSES THE INTERNAL FIELD DESIGNATOR TO INCREMENT.
5. IF SYSCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.
6. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
VD
HD
1
2
3
4
5
FALLING EDGE RESYNCS THE CIRCUIT TO THE LINE/PIXEL NUMBER 0. VD AND HD INTERNALLY RESYNC.
RISING EDGE RESETS COUNTERS.
VD IS DISABLED DURING SYNC. THE REGISTER IS PROGRAMMABLE.
SCP, HBLK, AND CLPOB ARE HELD AT SEQ0 VALUE.
XV1 TO XV24 SIGNALS ARE HELD AT THE V-OUTPUT START POLARITY.
7
Figure 80. Enhanced SYNC Mode 2 with Vertical Signals Held at VTP Start Value
1
3
4
5
Figure 79. Default Mode 1
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VDLEN
3
SUSPEND
2
5
AD9927