AD9927 Analog Devices, AD9927 Datasheet - Page 85

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

COMPLETE REGISTER LISTING
When an address contains less than 28 data bits, all remaining bits must be written as 0s.
Table 48. AFE Registers
Address
00
01
02
03
04
05
06
0D
Table 49. Miscellaneous Registers
Address
10
11
12
13
14
Data
Bits
[1:0]
[2]
[3]
[4]
[5]
[6]
[0]
[1]
[2]
[3]
[0]
[23:0]
[2:0]
[9:0]
[9:0]
[0]
Data
Bits
[0]
[0]
[0]
[4:1]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[12:8]
[13]
[14]
[0]
Default
Value
3
1
0
0
0
0
0
0
0
1
0
FFFFFF
0
F
1EC
0
Default
Value
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
Update
Type
SCK
SCK
SCK
SCK
VD
VD
VD
VD
Update
Type
SCK
VD
SCK
SCK
SCK
CLPENABLE
CLPSPEED
FASTUPDATE
VGAGAIN
CLAMPLEVEL
CLIDIVIDE
OUTCONTROL
SYNCPOL
ENH_SYNC_EN
SYNC_MASK_HD
SYNC_MASK_VD
SYNC_MASK_V
TEST
UPDATE_SHADOW
SWSYNC
Name
STANDBY
PBLK_LVL
DCBYP
DOUTDISABLE
DOUTLATCH
GRAY_EN
TEST
TEST
TEST
CDSGAIN
Name
SW_RST
RSTB_EN
TEST
SYNCENABLE
SYNCSUSPEND
SHADOW_EN
TGCORE_RSTB
Rev. 0 | Page 85 of 100
Description
Standby modes. 0: normal operation; 1: Standby1 mode;
2: Standby2 mode; 3: Standby3 mode.
0: disable OB clamp; 1: enable OB clamp.
0: select normal OB clamp settling; 1: select fast OB clamp settling.
0: ignore CDS gain; 1: very fast clamping when CDS gain is updated.
0: blank data outputs to 0 during PBLK;
1: blank data outputs to programmed clamp level during PBLK.
0: enable input dc restore circuit during PBLK;
1: disable input dc restore circuit during PBLK.
0: data outputs are driven; 1: data outputs are three-stated.
0: latch data outputs using the rising edge of DOUTPHASEP
(DOUTPHASEP register setting);
1: output latch is transparent.
1: enable gray encoding of the digital data outputs.
Set to 0.
Do not access, or set to 0.
Do not access, or set to 0xFFFFFF.
CDS gain setting. 0: −3 dB; 4: 0 dB; 6: +3 dB; 7: +6 dB.
All other values are invalid.
VGA gain, 6 dB to 42 dB (0.035 dB per step).
Optical black clamp level, 0 to 1023 LSB (1 LSB per step).
0: no division of CLI; 1: divide CLI input frequency by 2.
Description
Software reset. Bit self-clears to 0 when a reset occurs.
1: reset Address 0x00 to Address 0xFF to default values.
0: make all outputs dc inactive; 1: enable outputs at next VD
edge.
1: configure SYNC pin as RSTB input signal.
Test mode only. Must be set to 0.
1: external synchronization enable (configures Pin D3 as an
input).
SYNC active polarity.
Suspend clocks during SYNC active pulse. 0: don’t suspend;
1: suspend.
1: enable enhanced sync/shutter operations.
1: mask HD during SYNCSUSPEND.
1: mask VD during SYNCSUSPEND.
1: mask XV outputs during SYNCSUSPEND.
1: enable use of shadow registers.
Test mode only. Must be set to 0.
1: writes to shadow bits affect shadow registers, not primary.
1: initiate software SYNC event (self-clears to 0 after SYNC).
Timing core reset bar. 0: reset TG core; 1: resume operation.
AD9927