AD9882 Analog Devices, AD9882 Datasheet - Page 29

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

14
A bit that can put the outputs in a high impedance mode. This
applies to the 24 data output pins, HSOUT, VSOUT, and DE Pins.
PDO
0
1
The default for this register is 0. (This option works on both the analog and
digital interfaces.)
14
This bit is used to set the HDCP Slave Port address.
Address Bit
0
1
The default for this register is 0.
14
This bit is used to control chip power-down. See the section on
power management for details about which blocks are actually
powered down.
Select
0
1
The default for this register is 1.
14
A bit that configures the output data in 4:2:2 mode. This mode
can be used to reduce the number of data lines used from 24
to 16 for applications using YPbPr graphics signals. A timing
diagram for this mode is shown in Figure 9. Recommended
input and output configurations are shown in Table XXXVI.
In 4:2:2 mode, the RED and BLUE channels can be interchanged
to help satisfy board layout or timing requirements, but the
GREEN channel must be configured for Y.
Select
0
1
Channel
RED
GREEN
BLUE
REV. A
3
2
1
0
Table XXXVI. 4:2:2 Input/Output Configuration
Table XXXII. Power-Down Output Settings
Table XXXIII. HDCP Address Settings
Table XXXV. 4:2:2 Output Mode Select
PDO
HDCP Address
PWRDN
4:2:2 Output Mode Select
Table XXXIV. Power-Down Settings
Function
Normal operation
Three-state
Result
Power-down
Normal operation
Output Mode
4:4:4
4:2:2
Input Connection
Pr
Y
Pr
Result
0 for HDCP Slave Port
1 for HDCP Slave Port
Power-Down Outputs
Output Format
Pb/Pr
Y
High impedance
–29–
15
This bit is used to indicate when activity is detected on the
Hsync input pin (Pin 79). If Hsync is held high or low, activity
will not be detected.
Detect
0
1
The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.
15
This bit is used to indicate when sync activity is detected on the
Sync-on-Green input pin (Pin 64).
Detect
0
1
The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.
Note: If no Sync signal is presented on the GREEN video input,
normal video may still trigger activity.
15
This bit is used to indicate when activity is detected on the
Vsync input pin (Pin 80). If Vsync is held high or low, activity
will not be detected.
Detect
0
1
The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.
15
This bit is used to indicate when activity is detected on the
digital interface clock input.
Detect
0
1
The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.
Table XL. Digital Interface Clock Detection Results
7
6
Table XXXVIII. Sync-on-Green Detection Results
5
4
Table XXXVII. Hsync Detection Results
Table XXXIX. Vsync Detection Results
Hsync Detect
Sync-on-Green Detect
Vsync Detect
Digital Interface Clock Detect
Function
No activity detected
Activity detected
Function
No activity detected
Activity detected
Function
No activity detected
Activity detected
Function
No activity detected
Activity detected
AD9882