AD9882 Analog Devices, AD9882 Datasheet - Page 14

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

AD9882
Hsync, Vsync Inputs
The AD9882 receives a horizontal sync signal and uses it to
generate the pixel clock and clamp timing. This can be either a
sync signal directly from the graphics source or a preprocessed
TTL or CMOS level signal.
The Hsync input includes a Schmitt trigger buffer and is capable
of handling signals with long rise times, with superior noise
immunity. In typical PC based graphic systems, the sync signals
are simply TTL level drivers feeding unshielded wires in the
monitor cable. As such, no termination is required.
Serial Control Port
The serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150 W series resistors placed between the pull-up resistors and
the input pins.
Output Signal Handling
The digital outputs are designed and specified to operate from
a 3.3 V power supply (V
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board A/D
converters.
Most graphics systems produce RGB signals with black at ground
and white at approximately 0.75 V. However, if sync signals are
embedded in the graphics, the sync tip is often at ground and
black is at 300 mV; white will be approximately 1.0 V. Some
common RGB line amplifier boxes use emitter-follower buffers
to split signals and increase drive capability. This introduces a
700 mV dc offset to the signal, which is removed by clamping
for proper capture by the AD9882.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. Origi-
nating from CRT displays, the electron beam is “blanked” by
sending a black level during horizontal retrace to prevent
disturbing the image. Most graphics systems maintain this
format of sending a black level between active video lines.
An offset is then introduced, which results in the A/D converters
producing a black output (code 00H) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is virtually always
a period following Hsync called the back porch, in which a good
black reference is provided. This is the time when clamping should
be done.
The clamp timing is established by the AD9882 internal clamp
timing generator. The Clamp Placement Register (05H) is
programmed with the number of pixel times that should pass
after the trailing edge of Hsync before clamping starts. A second
register (Clamp Duration, 06H) sets the duration of the clamp.
DD
). They can also work with a V
DD
as
–14–
These are both 8-bit values, providing considerable flexibility in
clamp generation. The clamp timing is referenced to the trailing
edge of Hsync since the back porch (black reference) always
follows Hsync. A good starting point for establishing clamping is
to set the clamp placement to 08H (providing eight pixel periods
for the graphics signal to stabilize after sync) and set the clamp
duration to 14H (giving the clamp 20 pixel periods to re-establish
the black reference).
The value of the external input coupling capacitor affects the
performance of the clamp. If the value is too small, there can be
an amplitude change during a horizontal line time (between
clamping intervals). If the capacitor is too large, then it will take
excessively long for the clamp to recover from a large change in
incoming signal offset. The recommended value (47 nF) results
in recovery from a step error of 100 mV to within one-half LSB
in 10 lines using a clamp duration of 20 pixel periods on a 75 Hz
SXGA signal.
YUV Clamping
YUV signals are slightly different from RGB signals in that the
dc reference level (black level in RGB signals) will be at the
midpoint of the U and V video. For these signals, it can be
necessary to clamp to the midscale range of the A/D converter
range (80H) rather than the bottom of the A/D converter range (00H).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 11H and are Bits 4–6. The midscale
reference voltage that each A/D converter clamps to is provided
on the MIDBYPASS pin (Pin 74). This pin should be bypassed
to ground with a 0.1 mF capacitor (even if midscale clamping is
not required).
Gain and Offset Control
The AD9882 can accommodate input signals with inputs ranging
from 0.5 V to 1.0 V full scale. The full-scale range is set in three
8-bit registers (RED Gain, GREEN Gain, and BLUE Gain).
A code of 0 establishes a minimum input range of 0.5 V;
255 corresponds with the maximum range of 1.0 V. Note
that INCREASING the gain setting results in an image with
LESS contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (RED Offset,
GREEN Offset, BLUE Offset) provide independent settings
for each channel.
The offset controls provide a ± 63 LSB adjustment range. This
range is connected with the full-scale range, so if the input range
is doubled (from 0.5 V to 1.0 V), the offset step size is also
doubled (from 2 mV per step to 4 mV per step).
Figure 2 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional to
the full-scale range, so changing the full-scale range also changes
the offset. The change is minimal if the offset setting is near
midscale. When changing the offset, the full-scale range is not
affected, but the full-scale level is shifted by the same amount as
the zero-scale level.
REV. A