AD9882 Analog Devices, AD9882 Datasheet - Page 17

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

The COAST function allows the PLL to continue to run at the
same frequency, in the absence of the incoming Hsync signal or
during disturbances in Hsync (such as equalization pulses). This
may be used during the vertical sync period, or any other time
that the Hsync signal is unavailable. Also, the polarity of the
Hsync signal may be set through the Hsync Polarity Bit (Register
10H, Bit 6). If not using automatic polarity detection, the Hsync
polarity bit should be set to match the polarity of the Hsync
input signal.
TIMING (ANALOG INTERFACE)
The following timing diagrams show the operation of the AD9882.
The Output Data Clock signal is created so that its rising edge
always occurs between data transitions and can be used to latch
the output data externally.
Hsync Timing
Horizontal Sync (Hsync) is processed in the AD9882 to elimi-
nate ambiguity in the timing of the leading edge with respect to
the phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360∞ in 32 steps via the Phase Adjust
REV. A
DATACK
HSOUT
DATA
Figure 7. Output Timing
t
DCYCLE
t
SKEW
t
PER
–17–
Register (Register 04H) to optimize the pixel sampling time.
Display systems use Hsync to align memory and display write
cycles, so it is important to have a stable timing relationship
between Hsync output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9882. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (Register 10H, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via
Register 07H. HSOUT is the sync signal that should be used to
drive the rest of the display system.
Coast Timing
In most computer systems, the Hsync signal is provided continu-
ously on a dedicated wire. In these systems, the COAST function
is unnecessary and should be disabled using Register 11H, Bits 1–3.
In some systems, however, Hsync is disturbed during the Vertical
Sync period (Vsync). In other cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embedded Sync-on-Green (SOG), Hsync
includes equalization pulses or other distortions during Vsync. To
avoid upsetting the clock generator during Vsync, it is important
to ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it will attempt to lock to this new frequency and will
have changed frequency by the end of the Vsync period. It will
then take a few lines of correct Hsync timing to recover at the
beginning of a new frame, resulting in a “tearing” of the image
at the top of the display.
The COAST function is provided to eliminate this problem. It
is an internally generated signal, created by the sync processing
engine that disables the PLL input and allows the clock to free-run
at its then-current frequency. The PLL can free-run for several
lines without significant frequency drift.
AD9882