AD9882 Analog Devices, AD9882 Datasheet - Page 13

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

THEORY OF OPERATION (INTERFACE DETECTION)
Active Interface Detection and Selection
The AD9882 includes circuitry to detect whether an interface is
active or not. See Table III.
For detecting the analog interface, the circuitry monitors the
presence of Hsync, Vsync, and Sync-on-Green. The result of
the detection circuitry can be read from the 2-wire serial inter-
face bus at Address 15H, Bits 7, 5, and 6, respectively. If one of
these sync signals disappears, the maximum time it takes for the
circuitry to detect it is 100 ms.
For detecting the digital interface, there are two stages of detection.
The first stage searches for the presence of the digital interface
clock. The circuitry for detecting the digital interface clock is
active even when the digital interface is powered down. The
result of this detection stage can be read from the 2-wire serial
interface bus at Address 15H, Bit 4. If the clock disappears, the
maximum time it takes for the circuitry to detect it is 100 ms.
Once a digital interface clock is detected, the digital interface is
powered up and the second stage of detection begins. During
the second stage, the circuitry searches for 32 consecutive DEs.
Once 32 DEs are found, the detection process is complete.
There is an override for the automatic interface selection. It is
the AIO (Active Interface Override) bit, Register 0FH, Bit 2.
When the AIO bit is set to logic “0,” the automatic circuitry will
be used. When the AIO bit is set to logic “1,” the AIS (Active
Interface Select) bit (Register 0FH, Bit 1) will be used to
determine the active interface rather than the automatic circuitry.
Power Management
The AD9882 is a dual interface device with shared outputs. Only
one interface can be used at a time. For this reason, the chip auto-
matically powers down the unused interface. When the analog
interface is being used, most of the digital interface circuitry is
powered down, and vice versa. This helps to minimize the AD9882
total power dissipation. In addition, if neither interface has activity
on it, then the chip powers down both interfaces. The AD9882
uses the activity detect circuits, the active interface bits in Serial
Register 15H, the active interface override bits in Register 0FH,
Bits 2 and 1, and the power-down bit in Register 14H, Bit 1, to
determine the correct power state. In a given power mode, not all
circuitry in the inactive interface is powered down completely.
When the digital interface is active, the band gap reference
Hsync, Vsync, and SOG detect circuitry remain powered up.
When the analog interface is active, the digital interface clock
detect circuit is not powered down. Table IV summarizes how
the AD9882 determines what power mode to be in and what
circuitry is powered on/off in each of these modes. The power-
down command has priority, then the active interface override,
and then the automatic circuitry.
REV. A
–13–
THEORY OF OPERATION AND DESIGN GUIDE
(ANALOG INTERFACE)
General Description
The AD9882 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel
monitors or projectors. The device is ideal for implementing a
computer interface for HDTV monitors or as the front end to
high performance video scan converters.
Implemented in a high performance CMOS process, the inter-
face can capture signals with pixel rates of up to 140 MHz.
The AD9882 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface. Full integration of these sensitive analog
functions makes the system design straightforward and less
sensitive to the physical and electrical environment.
With a typical power dissipation of only 875 mW and an operat-
ing temperature range of 0∞C to 70∞C, the device requires no
special environmental considerations.
Input Signal Handling
The AD9882 has three high impedance analog input pins for
the RED, GREEN, and BLUE channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or BNC connectors.
The AD9882 should be located as close as practical to the input
connector. Signals should be routed via matched-impedance
traces (normally 75 W) to the IC input pins.
At that point, the signal should be resistively terminated (75 W
to the signal ground return) and capacitively coupled to the
AD9882 inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit. See Figure 1.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal band-
width. The wide bandwidth inputs of the AD9882 (300 MHz) can
track the input signal continuously as it moves from one pixel
level to the next and digitize the pixel during a long, flat pixel
time. In many systems, however, there are mismatches, reflections,
and noise, which can result in excessive ringing and distortion of
the input waveform. This makes it more difficult to establish a
sampling phase that provides good image quality. It has been
shown that a small inductor in series with the input is effective
in rolling off the input bandwidth slightly and providing a high
quality signal over a wider range of conditions. Using a Fair-Rite
#2508051217Z0 High Speed Signal Chip Bead inductor in the
circuit of Figure 1 gives good results in most applications.
Figure 1. Analog Input Interface Circuit
INPUT
RGB
75
47nF
R
G
B
AIN
AIN
AIN
AD9882