AD9882 Analog Devices, AD9882 Datasheet - Page 23

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

Hex
Address
10
11
12
13
14
REV. A
Read and Write
or Read Only
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
7–0
7–0
7–6
5
4
3
2
1
Default
Value
0*** ****
*1** ****
**0* ****
***0 ****
**** 0***
**** *0**
**** **0*
**** ***0
0*** ****
*0** ****
**0* ****
***0 ****
**** 1***
**** *0**
**** **1*
0000 0000
0000 0000
11** ****
**1* ****
***0 ****
**** 0***
**** *0**
**** **1*
Table IX. Control Register Map (continued)
Register Name
Hsync Polarity Override
Input Hsync Polarity
Output Hsync Polarity
Active Hsync Override
Active Hsync Select
Output Vsync Polarity
Active Vsync Override
Active Vsync Select
Clamp Function
Red Clamp Select
Green Clamp Select
Blue Clamp Select
Coast Select
Coast Polarity Override
Input Coast Polarity
Pre-Coast
Post-Coast
Output Drive Select
Programmable Bandwidth
DVI Clock Invert
DVI PDO Three-State
HDCP Address
Power-Down
–23–
0 = Full chip power-down
Function
0 = Polarity determined by chip
1 = Polarity set by 10H, Bit 6
0 = Active low polarity
1 = Active high polarity
0 = Active high sync signal
1 = Active low sync signal
0 = No override
1 = User overrides, analog Hsync set by 10H, Bit 3
0 = Analog Hsync from the Hsync input pin
1 = Analog Hsync from SOG
This bit is used if Register 10H, Bit 4 is set to
1 or if both syncs are active.
0 = Invert
1 = Not inverted
0 = No override
1 = User overrides, analog Vsync set by 10H, Bit 0
0 = Analog Vsync from the Vsync input pin
1 = Analog Vsync from sync separator
0 = Clamping with internal clamp
1 = Clamping disabled
0 = Clamp to ground
1 = Clamp to midscale for red channel
0 = Clamp to ground
1 = Clamp to midscale for green channel
0 = Clamp to ground
1 = Clamp to midscale for blue channel
0 = Disabled coast
1 = Coasting with internally generated coast signal
0 = Coast polarity determined by the chip
1 = Coast polarity set by 11H, Bit 1
This bit must be set to 1 to disable coast.
0 = Active low coast signal
1 = Active high coast signal
This bit must be set to 1 to disable coast.
Number of Hsync periods that coast goes active
prior to Vsync.
Number of Hsync periods before coast goes inactive
following Vsync.
Selects among high, medium, and low output
drive strength.
0 = Low bandwidth of 10 MHz
1 = High bandwidth of 300 MHz
0 = DVI data clock output not inverted
1 = DVI data clock output inverted
For digital interface only.
0 = Normal outputs
1 = High impedance outputs
Address Bit 0 = 0 for HDCP Slave Port
Address Bit 1 = 1 for HDCP Slave Port
AD9882