AD9882 Analog Devices, AD9882 Datasheet - Page 27

• Manufacturer Part Number: AD9882
• Description: Dual Interface for Flat Panel Displays
• Manufacturer: Analog Devices

Active HIGH means the leading edge of the Hsync pulse is
positive-going. This means that timing will be based on the
leading edge of Hsync, which is now the RISING edge.
The device will operate if this bit is set incorrectly, but the inter-
nally generated clamp position, as established by Clamp Placement
(Register 05H), will not be placed as expected, which may
generate clamping errors.
The power-up default value is HSPOL = 1.
10
One bit that determines the polarity of the Hsync output and the
SOG output. Table XVI shows the effect of this option. SYNC
indicates the logic state of the sync pulse.
Setting
0
1
The default setting for this register is 0.
10
This bit is used to override the automatic Hsync selection. To
override, set this bit to logic 1. When overriding, the active
Hsync is set via Bit 3 in this register.
Override
0
1
The default for this register is 0.
10
This bit is used under two conditions. It is used to select the active
Hsync when the override bit is set (Bit 4). Alternately, it is used
to determine the active Hsync when not overriding, but both
Hsyncs are detected.
Select
0
1
The default for this register is 0.
10
One bit that determines the polarity of the Vsync output.
Table XIX shows the effect of this option. SYNC indicates the
logic state of the sync pulse.
Setting
1
0
The default setting for this register is 0.
REV. A
5
4
3
2
Table XVII. Active Hsync Override Settings
Table XVI. Hsync Output Polarity Settings
Table XIX. Vsync Output Polarity Settings
Table XVIII. Active Hsync Select Settings
Hsync Output Polarity
Active Hsync Override
Active Hsync Select
Vsync Output Polarity
SYNC
Logic 1 (positive polarity)
Logic 0 (negative polarity)
Result
Autodetermine the active Hsync.
Override. Bit 3 determines the active Hsync.
Result
Hsync input
Sync-on-Green input
SYNC
Not invert
Invert
–27–
10
This bit is used to override the automatic Vsync selection. To
override, set this bit to logic 1. When overriding, the active
interface is set via Bit 0 in this register.
Override
0
1
The default for this register is 0.
10
This bit is used to select the active Vsync when the override bit
is set (Bit 1).
Select
0
1
The default for this register is 0.
11
A bit that enables/disables clamping.
Clamp Function
0
1
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and duration
is counted from the trailing edge of Hsync.
A 1 disables clamping. The three channels are clamped when
the CLAMP signal is active.
Power-up default value is CLAMP FUNCTION = 0.
11
A bit that determines whether the RED channel is clamped to
ground or to midscale. For RGB video, all three channels are
referenced to ground. For YPbPr, the Y channel is referenced
to ground, but the PbPr channels are referenced to midscale.
Clamping to midscale actually clamps to Pin 74.
Clamp
0
1
The default setting for this register is 0.
1
0
7
Table XXII. Clamp Input Signal Source Settings
6
Table XX. Active Vsync Override Settings
Table XXIII. RED Clamp Select Settings
Table XXI. Active Vsync Select Settings
Active Vsync Override
Active Vsync Select
Clamp Function
Result
Autodetermine the active Vsync
Override. Bit 0 determines the active Vsync.
Result
Vsync input
Sync separator output
Function
Clamp to ground
Clamp to midscale (Pin 74)
RED Clamp Select
Function
Internally generated clamp enabled
Clamping disabled
AD9882