P60ARM-B/IG/GP1N Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1N Datasheet - Page 71

• Manufacturer Part Number: P60ARM-B/IG/GP1N
• Description: A Low Power, General Purpose 32 Bit RISC Microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

If a byte write is requested (STRB), ARM60 will broadcast the byte value across the data bus, presenting it
at each byte location within the word. The memory system must decode A[1:0] to enable writing only to the
addressed byte.
One way of implementing the byte decode in a DRAM system is to separate the 32 bit wide block of DRAM
into four byte wide banks, and generate the column address strobes independently as shown in Figure 31:
Decoding Byte Accesses to Memory .
When the processor is configured for Little Endian operation byte 0 of the memory system should be
connected to data lines 7 through 0 ( D[7:0] ) and strobed by nCAS0 . nCAS1 drives the bank connected to
data lines 15 though 8, and so on. This has the added advantage of reducing the load on each column strobe
driver, which improves the precision of this time critical signal.
In the Big Endian case, byte 0 of the memory system should be connected to data lines 31 through 24
MCLK
A[31:0]
nMREQ
SEQ
nRAS
nCAS
D[31:0]
Figure 30: Memory Cycle Optimization
I-cycle
S-cycle
Memory Interface
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