P60ARM-B/IG/GP1N Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1N Datasheet - Page 16

• Manufacturer Part Number: P60ARM-B/IG/GP1N
• Description: A Low Power, General Purpose 32 Bit RISC Microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
The format of the Program Status Registers is shown in Figure 4: Format of the Program Status Registers
(PSRs) . The N, Z, C and V bits are the condition code flags . The condition code flags in the CPSR may be
changed as a result of arithmetic and logical operations in the processor and may be tested by all
instructions to determine if the instruction is to be executed.
The I and F bits are the interrupt disable bits. The I bit disables IRQ interrupts when it is set and the F bit
disables FIQ interrupts when it is set. The M0, M1, M2, M3 and M4 bits (M[4:0]) are the mode bits , and these
determine the mode in which the processor operates. The interpretation of the mode bits is shown in Table
2: The Mode Bits . Not all combinations of the mode bits define a valid processor mode. Only those explicitly
described shall be used.
The bottom 28 bits of a PSR (incorporating I, F and M[4:0]) are known collectively as the control bits . The
control bits will change when an exception arises and in addition can be manipulated by software when the
processor is in a privileged mode. Unused bits in the PSRs are reserved and their state shall be preserved
when changing the flag or control bits. Programs shall not rely on specific values from the reserved bits
when checking the PSR status, since they may read as one or zero in future processors.
12
31
N
30
Z
flags
M[4:0]
10000
10001
10010
10011
10111
11011
29
C
28
V
Figure 4: Format of the Program Status Registers (PSRs)
Supervisor
Undefined
Mode
Abort
User
27
IRQ
FIQ
.
Overflow
Carry / Borrow / Extend
Zero
Negative / Less Than
Table 2: The Mode Bits
PC, R14..R0
PC, R14_fiq..R8_fiq, R7..R0
PC, R14_irq..R13_irq, R12..R0
PC, R14_svc..R13_svc, R12..R0
PC, R14_abt..R13_abt, R12..R0
PC, R14_und..R13_und, R12..R0
.
8
.
7
I
Accessible register set
F
6
control
5
.
M4
4
CPSR, SPSR_fiq
CPSR, SPSR_irq
CPSR, SPSR_svc
CPSR, SPSR_abt
CPSR, SPSR_und
CPSR
M3
3
M2
2
M1
Mode bits
FIQ disable
IRQ disable
1
M0
0