T7256 Agere Systems, T7256 Datasheet - Page 55

• Manufacturer Part Number: T7256
• Description: (T7234 - T7256) Compliance
• Manufacturer: Agere Systems

Lucent Technologies Inc.
February 1998
Glossary
ACTMODE/INT:
ACTR:
ACTSC:
ACTSCM:
ACTSEL:
ACTT:
AFRST:
AIB:
ANSI:
ASI:
AUTOACT:
AUTOCTL:
AUTOEOC:
A[3:1]R:
A[3:1]T:
BERR:
BERRM:
CCRC:
CDM:
CFR0:
Act bit mode, serial interface
microprocessor interrupt.
Receive activation
(register CFR1, bit 0).
Activation/deactivation state
change on U-interface
(register UIR0, bit 1).
Activation/deactivation state
change on U-interface interrupt
mask (register UIR1, bit 1).
Act mode select (register
GR2, bit 6).
Transmit activation (register
GR1, bit 4).
Adaptive filter reset (register
CFR0, bit 1).
Alarm indication bit (register
CFR1, bit 6).
American National Standards In-
stitute.
Alternate space inversion.
Automatic activation control
(register GR0, bit 6).
Auto control enable
(register GR0, bit 3).
Automatic eoc processor
enable (register GR0, bit 4).
Receive eoc address (register
ECR2, bits 0—2).
Transmit eoc address
(register ECR0, bits 0—2).
Block error on U-interface
(register UIR0, bit 2).
Block error on U-interface inter-
rupt mask (register UIR1, bit 2).
Corrupt cyclic redundancy check
(register ECR0, bit 7).
Charged-device model.
Control flow state machine con-
trol—maintenance/reserved bits
register.
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
CFR1:
CFR2:
CKOUT:
CODEC:
CRATE[1:0]:
CRC:
DFR0:
DFR1:
DMR:
DMT:
DPGS:
ECR0:
ECR2:
ECR3:
EMINT:
EMINTM:
EOC:
EOCSC:
EOCSCM:
Control flow state machine status
register.
Control flow state machine
status—reserved bits register.
Clock output.
Coder/decoder, typically used for
analog-to-digital conversions or
digital-to-analog conversions.
CKOUT rate control (register
GR0, bits 2—1).
Cyclic redundancy check.
Data flow control—U and S/T
B-channels register.
Data flow control—D-channels
and TDM bus register.
Receive eoc data or message in-
dicator (register ECR2, bit 3).
Transmit eoc data or message in-
dicator (register ECR0, bit 3).
Digital pair gain system.
eoc state machine control—ad-
dress register.
eoc state machine status—ad-
dress register.
eoc state machine status—infor-
mation register.
Exit maintenance mode interrupt
(register MIR0, bit 2).
Exit maintenance mode interrupt
mask (register MIR1, bit 2).
Embedded operations channel.
eoc state change on U-interface
(register UIR0, bit 0).
eoc state change on U-interface
mask (register UIR1, bit 0).
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