T7256 Agere Systems, T7256 Datasheet - Page 11

• Manufacturer Part Number: T7256
• Description: (T7234 - T7256) Compliance
• Manufacturer: Agere Systems

Lucent Technologies Inc.
February 1998
Pin Information
Table 1. Pin Description (continued)
* I
25, 34,
40, 41
u
Pin
= input with internal pull-up; I
26
27
28
29
30
31
32
35
36
37
38
43
44
Symbol
RESET
SDINN
HIGHZ
SDINP
VRCM
GND
RNR
RPR
VRP
VRN
LON
LOP
HN
HP
A
Type*
(continued)
—
—
—
—
O
O
I
I
I
I
I
I
I
I
d
u
d
= input with internal pull-down.
Analog Ground. Ground leads for analog circuitry.
Receive Negative Rail for S/T-Interface. Negative input of S/T-interface analog re-
ceiver. Connect to transformer through a 10 k
Receive Positive Rail for S/T-Interface. Positive input of S/T-interface analog re-
ceiver. Connect to transformer through a 10 k
Common-Mode Voltage Reference for U-Interface Circuits. Connect a
0.1 F
Positive Voltage Reference for U-Interface Circuits. Connect a 0.1 F
pacitor to GND
Negative Voltage Reference for U-Interface Circuits. Connect a 0.1 F
pacitor to GND
Hybrid Negative Input for U-Interface. Connect directly to negative side of
U-interface transformer.
Line Driver Positive Output for U-Interface. Connect to the U-interface transformer
through a 16.9
Line Driver Negative Output for U-Interface. Connect to the U-interface transform-
er through a 16.9
Hybrid Positive Input for U-Interface. Connect directly to positive side of
U-interface transformer.
Sigma-Delta A/D Negative Input for U-Interface. Connect via an 820 pF
capacitor to SDINP.
Sigma-Delta A/D Positive Input for U-Interface. Connect via an 820 pF
capacitor to SDINN.
Reset (Active-Low). Asynchronous Schmitt trigger input. Reset halts data transmis-
sion, clears adaptive filter coefficients, resets the U-transceiver timing recovery cir-
cuitry, resets the S/T-interface transceiver, and sets all microprocessor register bits
to their default state. During reset, the U-interface transmitter produces 0 V and the
output impedance is 135
quiet mode maintenance testing (refer to pin 2 for more description). The states of
ACTMODE, SYN8K_CTL, and AUTOACT are read upon exiting reset state (see cor-
responding pin descriptions). An internal 100 k pull-down resistor is on this pin.
RESET must be held low for 1.5 ms after power-on. Device is fully functional after an
additional 1 ms.
High-Impedance Control (Active-Low). Control of the high-impedance function. An
internal 100 k pull-up resistor is on this pin. Note: This pin does not 3-state the an-
alog outputs.
0—All digital outputs enter high-impedance state.
1—No effect on device operation.
20% capacitor to GND
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
A
A
(as close to the device pins as possible).
(as close to the device pins as possible).
1% resistor.
1% resistor.
at tip and ring. The RESET pin can be used to implement
A
(as close to the device pins as possible).
Name/Function
10% resistor.
10% resistor.
20% ca-
5%
20% ca-
5%
7