T7256 Agere Systems, T7256 Datasheet - Page 39

• Manufacturer Part Number: T7256
• Description: (T7234 - T7256) Compliance
• Manufacturer: Agere Systems

Lucent Technologies Inc.
February 1998
Questions and Answers
U-Interface
Q19: I need a way to generate a scrambled 2B1Q data
A19: A scrambled 2B1Q data stream (the “SN1” signal
Q20: We are trying to do a return loss measurement on
A20: The return loss is only relevant when the trans-
stream from the T7234 for test purposes (e.g.,
ANSI T1.601 Section 5.3.2.2, Total Power and
Section 7.2, Longitudinal Output Voltage). How
can I do this?
described in ANSI T1.601 Table 5) can be gener-
ated by pulling ILOSS (pin 6) low on the T7234.
the U-interface of the T7234 per ANSI T1.601
Section 7.1. We are using a circuit similar to the
one you recommend in the data sheet. We have
observed the following. When the chip is in FULL
RESET mode (powered on but no activity on the
U- or S/T-interfaces), the return loss is very low,
i.e., the termination impedance appears to be
very large relative to 135
boundaries of Figure 19 of ANSI T1.601. How-
ever, if we inject a 10 kHz tone before making a
measurement, the return loss falls within the tem-
plate. Why is it necessary to inject the 10 kHz
tone in order to get this test to pass? Shouldn’t a
135
regardless of the state of the T7234 once it is
powered on?
mitter section is powered on. When the transmit-
ter is powered, it presents a low-impedance
output to the U-interface. The transmitter must be
held in this low-impedance state when the return
loss and longitudinal balance tests are per-
formed. This can be accomplished by pulling
RESET low (pin 43). With the RESET pin held
low, the transmitter is held in a low-impedance
state where each of its differential outputs drives
DV. In this state, it is prevented from transmitting
any 2BIQ data and won’t respond to any incom-
ing wakeup tones. This is different than the ANSI-
defined FULL RESET state that the chip enters
after power-on or deactivation. In FULL RESET,
the transmitter is powered down and in a high-
impedance state, with only the tone detector
powered on and looking for a far-end wakeup
tone. The transmitter powers down when in FULL
RESET state to save power and maximize the
tone detector sensitivity. The reason that the chip
behaves as it does in your tests is that your test
begins with the transmitter in its FULL RESET
state, causing the return loss to be very low. If a
10 kHz signal is applied, the tone detector
impedance be presented to the network
(continued)
and falls outside the
(continued)
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
Q21: What are the average cold start and warm start
A21: Lab measurements have shown the average cold
Q22: What is the U-interface’s response time to an
A22: Response time is about 1 ms.
Q23: What is the minimum time for a U-interface
A23: Five superframes (60 ms).
Q24: Where is the U-interface loopback 2 (i.e., eoc
A24: It is performed just inside the chip at the S/T-inter-
Q25: Are the embedded operations channel (EOC) ini-
A25: Yes, the B1 and B2 channel loopbacks are trans-
Q26: How can proprietary messages be passed across
A26: The embedded operations channel (EOC) pro-
senses the applied signal and triggers. This
causes the transmitter to enter its low-impedance
state, where it will remain until the T7234 start-up
state machine times out (typically within 1.5 sec-
onds, depending on the signal from the far end).
times?
start time to be about 3.3 s—4.2 s over all loop
lengths, and the average warm start time to be
around 125 ms—190 ms over all loop lengths.
incoming wakeup tone from the LT?
reframe after a momentary (<480 ms) loss of syn-
chronization?
2B+D loopback) performed in the T7234?
face. The S/T receiver is disconnected internally
from the chip pins, and the S/T transmit signal is
looped back to the receiver inputs so the S/T sec-
tion synchronizes to its own signal. This ensures
that as much of the data path as possible is being
tested during the 2B+D loopback.
tiated B1 and B2 channel loopbacks transparent?
parent, as is the 2B+D loopback.
the U-interface?
vides one way of doing this. ANSI standard
T1.601 defines 64 8-bit messages which can be
used for nonstandard applications. They range in
value from binary 00010000 to 01000000.
There is also a provision for sending bulk data
over the EOC. Setting the data/message indicator
bit to 0 indicates the current 8-bit EOC word con-
tains data that is to be passed transparently with-
out being acted on. Note that there is no
response time requirement placed on the NT in
this case (i.e., the NT does not have to echo the
message back to the LT). Also note that this is
currently only an ANSI provision and is not an
ANSI requirement. The T7234 does support this
provision.
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