T7256 Agere Systems, T7256 Datasheet - Page 51

• Manufacturer Part Number: T7256
• Description: (T7234 - T7256) Compliance
• Manufacturer: Agere Systems

Lucent Technologies Inc.
February 1998
Questions and Answers
S/T-Interface
Q35: In the Analog Interface section of the S/T-inter-
A35: The minimum value of 0 ms is necessary so that
Miscellaneous
Q36: Is the 100 ppm free-run frequency recommen-
A36: In the free-run mode, the output frequency is pri-
Q37: What happens if Co and Cm of the crystal differs
A37: None of the parameters should be varied. We
Q38: It has been noted in some other designs that the
face description in the data sheet, where does
the value of 0 ms—3.1 ms maximum differential
delay in adaptive timing mode come from?
the NT's transmitter and receiver can be directly
connected in a loopback and still synchronize.
The maximum value of 3.1 ms comes about
because the window size needed in the adaptive
timing algorithm is 2.1 ms. The window size is the
time during each bit period in which no transitions
may occur. Since a period is 5.2 ms, the time dur-
ing which there may be transitions is 5.2 ms –
2.1 ms, or 3.1 ms. This is the same as the maxi-
mum differential delay, since the earliest and lat-
est bit transitions represent the nearest and
farthest TEs relative to the NT receiver.
dation met in the T7234?
marily dependent on the crystal, not the silicon
design. For low-cost crystals, initial tolerance,
temperature, and aging effects may account for
two-thirds of this budget, and just a couple of pF
of variation in load capacitance will use up the
rest; therefore, the 100 ppm goal can be met if
the crystal parameters are well controlled. See
the Crystal Characteristics section in this data
sheet.
from the specification shown in the Crystal Char-
acteristics table?
have not characterized any such crystals, and
have no easy method of doing so. A crystal
whose parameters deviate from the requirements
may work in most applications but fail in isolated
cases involving certain loop configurations or
other system variations. Therefore, customers
choosing to vary any of these parameters do so
at their own risk.
crystal has a capacitor from each pin to ground.
Changing these capacitances allows the fre-
(continued)
(continued)
T7234 Single-Chip NT1 (SCNT1) Euro-LITE Transceiver
A38: For the T7234, these capacitors are located on
Q39: I plan to program the T7234 to output 15.36 MHz
A39: The 15.36 MHz output is a buffered version of the
Q40: How does the filtering at the OPTOIN input work?
A40: The signals applied to OPTOIN are digitally fil-
Q41: What is the isolation voltage of the 6N139
A41: 2500 Vac, 1 minute.
Q42: Can the T7234 operate with an external
A42: Yes, by leaving X1 disconnected and driving X2
Q43: What is the effect of ramping down the power-
A43: The device’s reset is more dependent on the
quency to be adjusted to compensate for board
parasitics. Can this be done with the T7234 crys-
tal? Also, can we use a crystal from our own
manufacturer?
the chip, so their values are fixed. The advantage
to this is that no external components are
required. The disadvantage is that board parasit-
ics must be very small. The Crystal Characteris-
tics section of the data sheet notes that the board
parasitics must be within the range of 0.6 pF
0.4 pF.
from its CKOUT pin. Is this clock a buffered ver-
sion of the 15.36 MHz oscillator clock? I am con-
cerned that if it is not buffered, the capacitive
loading on this pin could affect the system clock
frequency.
XTAL clock and therefore hanging capacitance
on it will not affect the T7234’s system clock fre-
quency.
tered for 20 ms. Any transitions under 20 ms will
be ignored.
optoisolator used in the dc termination circuit of
the T7234?
15.36 MHz clock source instead of using a crys-
tal?
with an external CMOS-level oscillator.
supply voltage on the device? When will it provide
a valid reset? This condition can occur when a
line-powered NT1’s line cord is repeatedly
plugged in and removed and plugged in again
before the power supply has had enough time to
fully ramp-up.
RESET pin than the power supply to the device.
As long as the proper input conditions on the
RESET pin (see Table 12) are met, the device will
have a valid reset. Note that this input is a
Schmitt-trigger input.
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