FM25C040 Fairchild Semiconductor, FM25C040 Datasheet - Page 9

• Manufacturer Part Number: FM25C040
• Description: 4K-Bit SPI Interface Serial CMOS EEPROM
• Manufacturer: Fairchild Semiconductor

FM25C040U Rev. B
The FM25C040U is also capable of a 4 byte PAGE WRITE
operation. Page write is performed similar to byte write operation
described above. During a Page write operation, after the first byte
of data, additional bytes (up to 3 bytes) can be input, before
bringing the /CS pin high to start the programming. After receipt of
each byte of data, the EEPROM internally increments the two low
order address bits (A1-A0) by one. The high order address bits
(A8-A2) will remain constant. If the master should transmit more
than 4 bytes of data, the address counter (A1-A0) will “roll over”
and the previously loaded data will be reloaded. See Figure 11.
FIGURE 11. Page Write
At the completion of a write cycle the EEPROM is automatically
returned to the write disabled state. Note that if the EEPROM is not
write enabled (WEN=0) before issuing the WRITE instruction, the
EEPROM will ignore the WRITE instruction and return to the
standby state when /CS is brought high.
WRITE STATUS REGISTER (WRSR):
The Write Status Register (WRSR) instruction provides write
access to the status register. This instruction is used to set Block
Write protection to a portion of the array as defined under Table
4. During a WRSR instruction only Bit3 (BP1) and Bit2 (BP0) can
be written with valid information while other bits are ignored.
Following is the format of WRSR data:
Status Register Write Data
X = Don’t Care
Note that the first four bits are don’t care bits followed by BP1 and
BP0 and two more don’t care bits.
WRSR instruction is enabled only when /WP pin is held high and
the EEPROM is write enabled previously (via WREN instruction).
WRSR command requires the following sequence. The /CS pin is
pulled low to select the EEPROM and then the WRSR opcode is
transmitted on the SI pin followed by the data to be programmed.
See Figure 12.
Bit
/CS
SO
X
7
SI
Bit
6
X
Op-Code
Write
Bit
X
5
Addr
Byte
Bit
4
X
Data
(1)
BP1
Bit
3
Data
(2)
BP0
Bit
2
Data
(3)
Bit
X
1
Data
(4)
Bit
0
X
9
FIGURE 12. Write Status Register
Programming will start after the /CS pin is forced back to a high
level. As in the WRITE instruction the LOW to HIGH transition of
the /CS pin must occur during the SCK low time immediately after
clocking in the last don’t care bit. See Figure 13.
FIGURE 13. Start WRSR Condition
At the completion of this instruction the EEPROM is automatically
returned to write disabled state.
INVALID OPCODE
If an invalid code is received, then no data is shifted into the
EEPROM, and the SO data output pin remains high impedance
state until a new /CS falling edge reinitializes the serial communi-
cation. See Figure 14.
FIGURE 14. Invalid Op-Code
/CS
SO
/CS
SO
SI
SI
SCK
/CS
SO
SI
BP0
Op-Code
WRSR
INVALID CODE
xxxxBP1BP0xx
SR Data
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