MX26F128J3 ETC-unknow, MX26F128J3 Datasheet - Page 21

• Manufacturer Part Number: MX26F128J3
• Description: Macronix Nbit Tm Memory Family 128m [x8/x16] Single 3v Page Mode Eliteflash Tm Memory
• Manufacturer: ETC-unknow

Read Configuration
The device will support both asynchronous page mode and standard word/byte reads. No configuration is required.
Status register and identifier only support standard word/byte single read operations.
Table 17. Read Configuration Register Definition
P/N:PM0960
Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has
been configured, it remains in that configuration until another configuration command is issued or RP is asserted low.
Initially, the STS pin defaults to RY/BY operation where RY/BY low indicates that the state machine is busy. RY/BY
high indicates that the state machine is ready for a new operation. Table 19, "Configuration Coding Definitions" on
page 28 displays the possible STS configurations.
To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired
configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described
below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete
interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the
default RY/BY level mode. The possible configurations and their usage are described in Table 19, "Configuration
Coding Definitions" on page 28. The Configuration command may only be given when the device is not busy. Check
SR.7 for device status. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set
to "1". When configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
RM
16(A16)
R
8
RCR.16 = READ MODE (RM)
0 = Standard Word/Byte Reads Enabled (Default)
1 = Page-Mode Reads Enabled
RCR.15-1= RESERVED FOR FUTURE
ENHANCEMENTS (R)
R
15
R
7
R
14
R
6
R
13
R
5
21
R
12
R
4
Notes
eLiteFlash
standard word/byte read cycles.
These bits are reserved for future use. Set these
bits to "0".
Read mode configuration effects reads from the
Status register, query, and identifier reads support
MX26F128J3
TM
memory array.
R
11
R
3
R
10
R
2
REV. 1.1,OCT. 18, 2004
R
9
R
1