MX26F128J3 ETC-unknow, MX26F128J3 Datasheet
MX26F128J3
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MX26F128J3 Summary of contents
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... High Performance - Block erase time: 2s typ. - Byte programming time: 210us typ. - Block programming time: 0.8s typ. (using Write to Buffer Command) • Program/Erase Endurance cycles: 100 cycles P/N:PM0960 MX26F128J3 TM Macronix NBit Software Feature • Support Common Flash Interface (CFI) - eLiteFlash TM memory device parameters stored on the device and provide the host system to access ...
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... GENERAL DESCRIPTION The MXIC's MX26F128J3 series eLiteFlash use the most advance 2 bits/cell Nbit technology, double the storage capacity of memory cell. The device provide the high density eLiteFlash TM memory solution with reli- able performance and most cost-effective. The device organized bits bits of output bus ...
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... SYMBOL PIN NAME A0 Byte Select Address A1~A23 Address Input Q0~Q15 Data Inputs/Outputs CE0, CE1, CE2 Chip Enable Input WE Write Enable Input OE Output Enable Input RESET Reset/Power Down mode P/N:PM0960 MX26F128J3 VPEN A13 VCC A18 GND A9 CE0 A14 ...
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... BLOCK DIAGRAM CE0 CE1 CONTROL CE2 INPUT OE WE LOGIC RESET ADDRESS LATCH A0-A23 AND BUFFER Q0-Q15 P/N:PM0960 MX26F128J3 PROGRAM/ERASE HIGH VOLTAGE ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 4 WRITE STATE MACHINE (WSM) STATE REGISTER COMMAND ...
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... VIH VIH VIL VIL VIH VIL VIH VIH VIH VIL VIH VIH VIH NOTE: For Single-chip applications, CE2 and CE1 can be strapped to GND. P/N:PM0960 MX26F128J3 A[23-1]: 128Mbit 7FFFFF 127 64-Kword Block 7F0000 3FFFFF 63 64-Kword Block 3F0000 1FFFFF 31 64-Kword Block 1F0000 01FFFF 1 64-Kword Block ...
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... See Section , "Read Query Mode Command" for read query data. 10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN= VPENH and VCC is within specification. 11.Refer to Table 3 on page 10 for valid DIN during a write operation. P/N:PM0960 MX26F128J3 Standby RESET Read ID Read Mode/ Query Power ...
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... OUTPUT DISABLE When VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. P/N:PM0960 MX26F128J3 STANDBY When CE0, CE1 and CE2 disable the device (see table1) and place it in standby mode. The power consumption of this device is reduced. Data input/output are in a high- impedance(High-Z) state ...
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... Notes Bus Write Cycles Req'd 2 First Bus Operation(2) Write Write Cycle Address(3) X Data(4,5) B8H Second Bus Operation(2) Write Write Cycle Address(3) X Data(4,5) CC P/N:PM0960 MX26F128J3 Read Read Read Clear ID Query Status Status Register Register 5 6 > 2 > Write Write Write ...
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... The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued. 10.Attempts to issue a block erase or program to a locked block. 11.Either 40H or 10H are recognized by the WSM as the byte/word program setup. 12.The clear block lock-bits operation simultaneously clears all block lock-bits. P/N:PM0960 MX26F128J3 9 REV. 1.1,OCT. 18, 2004 ...
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... Reserved for Future Implementation Block 31 Lock Configuration Reserved for Future Implementation (Block 2 through 30) Block 1 Reserved for Future Implementation Block 1 Lock Configuration Reserved for Future Implementation Block 0 Reserved for Future Implementation Block 0 Lock Configuration Device Code Manufacturer Code 10 MX26F128J3 REV. 1.1,OCT. 18, 2004 ...
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... ASCII "Q" in the low byte (DQ 0-7 ) and 00h in the high byte (DQ 8- Query addresses containing two or more bytes of in- formation, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. P/N:PM0960 TM memory TM memory com- 11 MX26F128J3 REV. 1.1,OCT. 18, 2004 ...
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... PrVendor 23h ID# 24h PrVendor 25h TblAdr 26h AltVendor 27h ID# 28h ... ... 12 MX26F128J3 Query data with byte addressing Hex Hex ASCII Offset Code Value 20: 51 "Q" 21: 00 "Null" 22: 52 "R" 20: 51 "Q" ...
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... Unlocked 1 = Locked BSR 1-7: Reserved for Future Use NOTE The beginning location of a Block Address (i.e., 008000h is block 1s (64-KB block) beginning location in word mode). P/N:PM0960 MX26F128J3 TM memory component to display the Common Flash Interface (CFI) Name Description Manufacturer Code Device Code Block-Specific Information Reserved for Vendor-Specific Information ...
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... P/N:PM0960 MX26F128J3 Add. 10 11: 12: 13: 14: 15: 16: 17: 18: ...
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... Device Geometry Definition Address 128M 27: --18 28: --02 29: --00 2A: --05 2B: --00 2C: --01 2D: --7F 2E: --00 2F: --00 30: --02 P/N:PM0960 MX26F128J3 TM memory device geometry number of bytes n 15 Code See Table Below 27: 28: --02 x8/x16 29: --00 2A: --05 32 2B: --00 2C: --01 1 2D: 2E: ...
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... VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts NOTE: 1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0". P/N:PM0960 MX26F128J3 TM memory Features and Commands) 16 Add. Hex Value Code ...
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... Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. (P+15)h Reserved for future use NOTE: 1. The variable pointer which is defined at CFI offset 15h. P/N:PM0960 MX26F128J3 TM memory Features and Commands factory pre-programmed bytes n = user-programmable bytes TM memory Features and Commands) ...
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... To activate this mode, the two cycle "Silicon ID Read" command is requested. (The command sequence is il- lustrated in Table 14. Table 14. MX26F128J3 Silicon ID Codes and Verify Sector Protect Code Type Manufacture Code Device Code Block Lock Configuration ...
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... Yes RESERVED XSR.0 Notes: 1. After a Buffer-Write command, XSR indicates that a Write Buffer is available. 2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register. P/N:PM0960 MX26F128J3 Definition "1" "0" Ready Busy Error in Block Erasure or Successful Block ...
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... CUI remains in read status register mode until a new command is issued. Also, reliable block erasure can only occur when VCC is valid and VPEN = VPENH. P/N:PM0960 MX26F128J3 WRITE TO BUFFER COMMAND To program the device, a Write to Buffer command is issue first. A variable number of bytes the buffer ...
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... Coding Definitions" on page 28. The Configuration command may only be given when the device is not busy. Check SR.7 for device status. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set to "1". When configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns. P/N:PM0960 MX26F128J3 ...
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... ER/PR INT (Erase or Program Interrupt): B8h, 03h Pulse-on-Erase or Program Complete NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns. P/N:PM0960 MX26F128J3 Pulse on Program Complete (1) bit are reserved for future use. ...
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... The device is switched to this mode by writing the Read Identifier command 90H. Once in this mode, read cycles from addresses retrieve the specified informa- P/N:PM0960 MX26F128J3 tion. To return to read array mode, write the Read Array command (FFH). Programming the Protection Register The protection register bits are programmed using the two-cycle Protection Program command ...
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... NOTE not used in x16 mode when accessing the protection register map (See Table 20 for x16 addressing). For x8 mode used (See Table 21 for x8 addressing). P/N:PM0960 MX26F128J3 A[23 -1]: 128 Mbit 4 Words User Programmed 4 Words Factory Programmed 1 Word Lock 24 REV ...
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... MX26F128J3 ...
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... Fill write buffer up to word count - Address=Address(es) within buffer range - Data=Data to be written Confirm Cycle - Issue Confirm Command - Address=Any address in block - Data=0xD0 Read Status Register See Status Register Flowchart P/N:PM0960 MX26F128J3 Start NO NO Write to Buffer D7=1? Time-Out ? YES YES Error-Handler Any Errors? ...
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... See Suspend/Resume Flowchart Program Suspend SR2 = '1' See Suspend/Resume Flowchart SR5 = '1' SR4 = ' Error Erase Failure Y es Error SR4 = '1' Program Failure Error SR3 = '1' V < V PEN PENLK Error SR1 = '1' Block Locked No End 27 MX26F128J3 Y es Error Command Sequence REV. 1.1,OCT. 18, 2004 ...
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... SR.4, SR.3, and SR.1 are only cleared by the Clear Status Register Command in cases where multiple lo- cation are programmed before full status is checked error is detected, clear the status register before attempting retry or other error recovery. 28 MX26F128J3 Comments Data=40H Programmed Data=Data to Be Programmed Addr=Location to Be ...
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... Figure 7. Block Erase Flowchart P/N:PM0960 MX26F128J3 Start Write 20H to Block Address Write Confirm D0H to Block Address Read Status Register NO SR.7=1 ? YES Full Status Check If Desired TM Erase eLiteFlash memory Block(s) Completed 29 REV. 1.1,OCT. 18, 2004 ...
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... Write 01H, Block Address Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed Read Status Register Data (See Above) NO Voltage Range Error SR.3=0 ? YES YES SR.4,5=1 ? Command Sequence Error NO NO Set Lock-Bit Error SR.4=0 ? YES Set Lock-Bit Successful 30 MX26F128J3 REV. 1.1,OCT. 18, 2004 ...
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... Write D0H Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed Read Status Register Data (See Above) NO Voltage Range Error SR.3=0 ? YES YES SR.4,5=1 ? Command Sequence Error NO NO SR.5=0 ? Clear Block Lock-Bits Error YES Clear Block Lock-Bit Successful 31 MX26F128J3 REV. 1.1,OCT. 18, 2004 ...
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... Figure 10. Protection Register Programming Flowchart FULL STATUS CHECK PROCEDURE P/N:PM0960 MX26F128J3 Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Program Completed Read Status Register Data (See Above) 1,1 VPEN Range Error SR ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. P/N:PM0960 MX26F128J3 OPERATING RATINGS Commercial (C) Devices +150 o C ...
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... VCC Power-Down Current ICC3 VCC Page Mode Read Current ICC5 VCC Program or Set Lock-Bit Current ICC6 VCC Block Erase or Clear Block Lock-Bits Current P/N:PM0960 MX26F128J3 Notes Typ Max Unit Test Conditions VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND ...
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... VPENLK (max) and VPENH (min), and above VPENH (max). 6. Typically, VPEN is connected to VCC (3 3.6 V). 7. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO , and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max). P/N:PM0960 MX26F128J3 Notes Min Max Unit 3 -0 ...
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... Input timing being, and output timing ends, at VCCQ/2V (50% of VCCQ). Input rise and fall times (10% tp 90%)<5ns. Figure 12. Transient Equivalent Testing Load Circuit Device Under Test NOTE: CL Includes Jig Capacitance Test Configuration C L (pF) VCCQ = VCC = 3.0 V-3 P/N:PM0960 MX26F128J3 VCCQ/2 Output TEST POINTS 1.3V 1N914 RL=3.3K ohm Out CL 36 REV. 1.1,OCT. 18, 2004 ...
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... When reading the eLiteFlash TM memory array a faster tGLQV (R16) applies. Non-array reads refer to status register reads, query reads, or device identifier reads. 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV). P/N:PM0960 MX26F128J3 VCC 3.0V-3.6V(3) VCCQ 3.0V-3.6V(3) 120 Notes ...
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... P/N:PM0960 tAVAV Valid Address Valid Address Valid Address tAVQV tELQV tGLQV tAPA tELQX Valid Valid Valid Output Output Output tGLQX tFLQV/tFHQV tFLQZ 38 MX26F128J3 Valid Address tEHEL tEHQZ tGHQZ tOH High Z Valid Output high is defined at the first X REV. 1.1,OCT. 18, 2004 ...
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... For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY default mode. 9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5=0). P/N:PM0960 MX26F128J3 Valid for All Speeds Notes Min ...
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... Automated erase delay. e. Read status register or query data. f. Write Read Array command. P/N:PM0960 AIN AIN tWHAX (tEHAX) tWHGL tWHEH (tEHGL) (tEHWH) tWPH tWHQZ/tWHRH tWHDX (tEHDX) DIN DIN tWHRL (tEHRL) tVPWH (tVPEH) 40 MX26F128J3 E F Valid DIN SRD tQVVL REV. 1.1,OCT. 18, 2004 ...
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... If RESET is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RESET Pulse Low Time is 100ns reset time, tPHQV, is required from the latter of STS (in RY/BY mode) or RESET going high until outputs are valid. P/N:PM0960 tPHRH tPLPH 41 MX26F128J3 Notes Min Max Unit ...
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... Parameter Symbol Parameter Description CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Notes: 1. Sampled, not 100% tested. 2. Test conditions TA=25 C, f=1.0MHz DATA RETENTION Parameter Minimum Pattern Data Retention Time P/N:PM0960 MX26F128J3 LIMITS MIN. TYP.(2) 2.0 218 210 0.8 100 MIN. -1.0V -1.0V -1.0V -100mA Test Set ...
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... ORDERING INFORMATION PLASTIC PACKAGE Part NO. MX26F128J3TC-12 MX26F128J3XCC-12 MX26F128J3TC-15 MX26F128J3XCC-15 P/N:PM0960 Access Time Package type (ns) 120/25 56-TSOP 120/25 64-CSP 150/25 56-TSOP 150/25 64-CSP 43 MX26F128J3 REV. 1.1,OCT. 18, 2004 ...
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... PACKAGE INFORMATION P/N:PM0960 MX26F128J3 44 REV. 1.1,OCT. 18, 2004 ...
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... P/N:PM0960 MX26F128J3 45 REV. 1.1,OCT. 18, 2004 ...
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... REVISION HISTORY Revision No. Description 1.0 1. Removed Part No. MX26F640J3 2. To add "eLiteFlash 1 add 120ns speed grade P/N:PM0960 MX26F128J3 TM TM " and "NBit " trademark 46 Page Date All JUN/30/2004 All P1,37,43 OCT/18/2004 REV. 1.1,OCT. 18, 2004 ...
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... MX26F128J3 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...