MBM29PDS322TE Fujitsu Microelectronics, Inc., MBM29PDS322TE Datasheet - Page 33

• Manufacturer Part Number: MBM29PDS322TE
• Description: Flash Memory 32m 2m X 16 Bit Page Dual Operation
• Manufacturer: Fujitsu Microelectronics, Inc.

Data Protection
Power On/Off Timing
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power up device automatically resets internal state
machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs
after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
and power-down transitions or system noise.
The RESET pin must be held low during V
(Refer to Figure 5.3.)
Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE = V
must be a logical zero while OE is a logical one.
Power-up of the device with WE = CE = V
The internal state machine is automatically reset to the read mode on power-up.
IL
CC
and OE = V
ramp up to insure that device power up correctly.
IL
, CE = V
MBM29PDS322TE/BE
IH
will not accept commands on the rising edge of WE.
IH
, or WE = V
IH
. To initiate a write cycle CE and WE
CC
power-up
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