MBM29PDS322TE Fujitsu Microelectronics, Inc., MBM29PDS322TE Datasheet - Page 30

• Manufacturer Part Number: MBM29PDS322TE
• Description: Flash Memory 32m 2m X 16 Bit Page Dual Operation
• Manufacturer: Fujitsu Microelectronics, Inc.

30
MBM29PDS322TE/BE
DQ
Data Polling
DQ
Toggle Bit I
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm an attempt to read device will produce a
complement of data last written to DQ
read device will produce true data last written to DQ
device will produce a “0” at the DQ
read device will produce a “1” on DQ
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected
sectors. Otherwise, the status may be invalid.
If a program address falls within a protected sector, Data Polling on DQ
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
Once the Embedded Algorithm operation is close to completion, the device data pins (DQ
chronously while the output enable (OE) is asserted low. This means that device is driving status information
on DQ
system samples the DQ
Algorithm operation and DQ
on DQ
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 9.)
See Figure 10 for the Data Polling timing specifications and diagrams.
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the
device will results in DQ
is completed, DQ
gramming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 1 s and then stop
toggling with data unchanged. In erase, device will erase all selected sectors except for ones that are protected.
If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into
read mode, having data unchanged.
Either CE or OE toggling will cause DQ
DQ
The system can use DQ
is actively erased (that is, the Embedded Erase Algorithm is in progress), DQ
Erase Suspend mode, DQ
to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
7
6
6
to toggle.
7
0
at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the
to DQ
7
will be read on the successive read attempts.
6
will stop toggling and valid data will be read on the next successive attempts. During pro-
6
7
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle
output, it may read the status or valid data. Even if device has completed the Embedded
to determine whether a sector is actively erased or is erase-suspended. When a bank
6
stops toggling. Successive read cycles during erase-suspend-program cause DQ
7
has a valid data, data outputs on DQ
7
output. Upon completion of the Embedded Erase Algorithm an attempt to
7
. The flowchart for Data Polling (DQ
7
6
. Upon completion of the Embedded Program Algorithm, an attempt to
to toggle. In addition, an Erase Suspend/Resume command will cause
7
is active for approximately 400 s, then the bank returns to read mode.
10/11
7
. During the Embedded Erase Algorithm, an attempt to read
0
to DQ
7
is active for approximately 1 s, then
7
) is shown in Figure 23.
6
may be still invalid. The valid data
6
toggles. When a bank enters the
7
) may change asyn-
6