RFPIC12C509AG Microchip Technology Inc., RFPIC12C509AG Datasheet - Page 31

• Manufacturer Part Number: RFPIC12C509AG
• Description: 18/20-pin 8-bit Cmos Microcontroller With Uhf Ask/fsk Transmitter
• Manufacturer: Microchip Technology Inc.

6.1
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (T
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
6.1.1
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-4).
Therefore, it is necessary for T0CKI to be high for at
least 2T
at least 2T
to the electrical specification of the desired device.
FIGURE 6-4:
©
2001 Microchip Technology Inc.
Note 1:
OSC
Using Timer0 with an External
Clock
2:
3:
OSC
EXTERNAL CLOCK
SYNCHRONIZATION
External Clock/Prescaler
Output After Sampling
(and a small RC delay of 20 ns) and low for
Increment Timer0 (Q4)
Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input =
External clock if no prescaler selected, Prescaler output otherwise.
The arrows indicate the points in time where sampling occurs.
Prescaler Output (2)
External Clock Input or
(and a small RC delay of 20 ns). Refer
TIMER0 TIMING WITH EXTERNAL CLOCK
Timer0
OSC
(3)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
) synchroniza-
(1)
Preliminary
T0
rfPIC12C509AG/509AF
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type pres-
caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4T
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
6.1.2
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 6-4 shows the delay
from the external clock edge to the timer incrementing.
6.1.3
If the option register is set to read TIMER0 from the pin,
the port is forced to an input regardless of the TRIS reg-
ister setting.
OSC
TIMER0 INCREMENT DELAY
OPTION REGISTER EFFECT ON
GP2 TRIS
(and a small RC delay of 40 ns) divided by
T0 + 1
4Tosc max.
T0 + 2
Small pulse
misses sampling
DS70031A-page 29