RFPIC12C509AG Microchip Technology Inc., RFPIC12C509AG Datasheet - Page 15

• Manufacturer Part Number: RFPIC12C509AG
• Description: 18/20-pin 8-bit Cmos Microcontroller With Uhf Ask/fsk Transmitter
• Manufacturer: Microchip Technology Inc.

3.3
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter is incremented every Q1, and the instruc-
tion is fetched from program memory and latched into
instruction register in Q4. It is decoded and executed
during the following Q1 through Q4. The clocks and
instruction execution flow is shown in Figure 3-2 and
Example 3-1.
FIGURE 3-2:
EXAMPLE 3-1:
©
1. MOVLW 03H
2. MOVWF GPIO
3. CALL
4. BSF
2001 Microchip Technology Inc.
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
Clocking Scheme/Instruction
Cycle
SUB_1
GPIO, BIT1
OSC1
PC
Q1
Q2
Q3
Q4
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
PC
Q3
Execute 1
Q4
Fetch 2
Preliminary
Q1
Execute INST (PC)
Fetch INST (PC+1)
Execute 2
Q2
Fetch 3
rfPIC12C509AG/509AF
PC+1
3.4
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Execute 3
Q4
Fetch 4
Instruction Flow/Pipelining
Q1
Fetch SUB_1 Execute SUB_1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
Flush
PC+2
Q3
Q4
DS70031A-page 13
Internal
phase
clock