DSPIC30F5013 Microchip Technology Inc., DSPIC30F5013 Datasheet - Page 62

• Manufacturer Part Number: DSPIC30F5013
• Description: Dspic30f5011/5013 High-performance Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC30F5011/5013
FIGURE 8-2:
8.2
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (V
converted.
When reading the Port register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an ana-
log input. Analog levels on any pin that is defined as a
digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
DS70116F-page 60
Configuring Analog Port Pins
Data Bus
WR TRIS
WR LAT +
WR Port
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Read Port
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Read TRIS
Peripheral Module
PIO Module
OH
Read LAT
TRIS Latch
Data Latch
D
D
or V
CK
CK
OL
Q
Q
) will be
8.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 8-1:
MOV
MOV
NOP
btss
1
0
1
0
0xFF00, W0
W0, TRISB
PORTB, #13
Output Enable
Output Data
I/O PORT WRITE/READ TIMING
Output Multiplexers
Input Data
; additional instruction
; Configure PORTB<15:8>
; as inputs
; and PORTB<7:0> as outputs
; bit test RB13 and skip if
PORT WRITE/READ
EXAMPLE
I/O Cell
© 2006 Microchip Technology Inc.
cycle
set
I/O Pad