DSPIC30F5013 Microchip Technology Inc., DSPIC30F5013 Datasheet - Page 217

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DSPIC30F5013

Manufacturer Part Number
DSPIC30F5013
Description
Dspic30f5011/5013 High-performance Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet

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I
I/O Ports .............................................................................. 59
I
I
I
I
I
I
Idle Current (I
In-Circuit Serial Programming (ICSP) ......................... 47, 139
Input Capture (CAPX) Timing Characteristics .................. 186
Input Capture Module ......................................................... 79
Input Capture Operation During Sleep and Idle Modes ...... 80
Input Capture Timing Requirements ................................. 186
Input Change Notification Module ....................................... 63
Instruction Addressing Modes............................................. 35
© 2006 Microchip Technology Inc.
2
2
2
2
2
2
C 10-bit Slave Mode Operation ........................................ 93
C 7-bit Slave Mode Operation .......................................... 93
C Master Mode Operation ................................................ 95
C Master Mode Support ................................................... 95
C Module .......................................................................... 91
S Mode Operation .......................................................... 127
Parallel (PIO) .............................................................. 59
Reception.................................................................... 94
Transmission............................................................... 94
Reception.................................................................... 93
Transmission............................................................... 93
Baud Rate Generator.................................................. 96
Clock Arbitration.......................................................... 96
Multi-Master Communication, Bus Collision and
Reception.................................................................... 95
Transmission............................................................... 95
Addresses ................................................................... 93
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................... 95
Interrupts..................................................................... 95
IPMI Support ............................................................... 95
Operating Function Description .................................. 91
Operation During CPU Sleep and Idle Modes ............ 96
Pin Configuration ........................................................ 91
Programmer’s Model................................................... 91
Register Map............................................................... 97
Registers..................................................................... 91
Slope Control .............................................................. 95
Software Controlled Clock Stretching (STREN = 1).... 94
Various Modes ............................................................ 91
Data Justification....................................................... 127
Frame and Data Word Length Selection................... 127
Interrupts..................................................................... 80
Register Map............................................................... 81
CPU Idle Mode............................................................ 80
CPU Sleep Mode ........................................................ 80
dsPIC30F5011 Register Map (Bits 15-8) .................... 63
dsPIC30F5011 Register Map (Bits 7-0) ...................... 63
dsPIC30F5013 Register Map (Bits 15-8) .................... 63
dsPIC30F5013 Register Map (Bits 7-0) ...................... 63
File Register Instructions ............................................ 35
Fundamental Modes Supported.................................. 35
MAC Instructions......................................................... 36
MCU Instructions ........................................................ 35
Move and Accumulator Instructions............................ 36
Other Instructions........................................................ 36
Bus Arbitration .................................................... 96
Master Mode ..................................................... 197
Slave Mode ....................................................... 199
Master Mode ..................................................... 198
Slave Mode ....................................................... 200
Master Mode ..................................................... 197
Slave Mode ....................................................... 199
IDLE
) ............................................................ 170
Instruction Set
Internal Clock Timing Examples ....................................... 178
Internet Address ............................................................... 219
Interrupt Controller
Interrupt Priority .................................................................. 42
Interrupt Sequence ............................................................. 45
Interrupts ............................................................................ 41
L
Load Conditions................................................................ 176
Low Voltage Detect (LVD) ................................................ 150
Low-Voltage Detect Characteristics.................................. 173
LVDL Characteristics ........................................................ 174
M
Memory Organization ......................................................... 23
Microchip Internet Web Site.............................................. 219
Modes of Operation
Modulo Addressing ............................................................. 36
MPLAB ASM30 Assembler, Linker, Librarian ................... 164
MPLAB ICD 2 In-Circuit Debugger ................................... 165
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development Environment Software.. 163
MPLAB PM3 Device Programmer .................................... 165
MPLINK Object Linker/MPLIB Object Librarian ................ 164
N
NVM
O
OC/PWM Module Timing Characteristics ......................... 188
Operating Current (I
Oscillator
Oscillator Selection ........................................................... 139
dsPIC30F5011/5013
Overview................................................................... 158
Summary .................................................................. 155
Register Map .............................................................. 46
Traps .......................................................................... 43
Interrupt Stack Frame................................................. 45
Core Register Map ..................................................... 32
Disable...................................................................... 109
Initialization............................................................... 109
Listen All Messages.................................................. 109
Listen Only................................................................ 109
Loopback .................................................................. 109
Normal Operation ..................................................... 109
Applicability................................................................. 38
Incrementing Buffer Operation Example .................... 37
Start and End Address ............................................... 37
W Address Register Selection.................................... 37
In-Circuit Emulator.................................................... 165
In-Circuit Emulator.................................................... 165
Register Map .............................................................. 51
Configurations .......................................................... 142
Operating Modes (Table).......................................... 140
System Overview...................................................... 139
Fail-Safe Clock Monitor .................................... 144
Fast RC (FRC).................................................. 143
Initial Clock Source Selection ........................... 142
Low Power RC (LPRC)..................................... 143
LP Oscillator Control......................................... 142
Phase Locked Loop (PLL) ................................ 143
Start-up Timer (OST)........................................ 142
DD
) .................................................... 169
DS70116F-page 215

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