DSPIC33FJ64MC508 Microchip Technology Inc., DSPIC33FJ64MC508 Datasheet - Page 58

• Manufacturer Part Number: DSPIC33FJ64MC508
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

TABLE 3-30:
TABLE 3-31:
TABLE 3-32:
RCON
OSCCON
CLKDIV
PLLFBD
OSCTUN
Legend:
Note
NVMCON
NVMKEY
Legend:
Note
File Name
File Name
TRISG
PORTG
LATG
ODCG
Legend:
Note
File Name
1:
2:
1:
1:
Addr
0742
0744
0746
0748
0740
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and type of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
Addr
02E4
02E6
02E8
06E4
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
Addr
0760
0766
PORTG REGISTER MAP
SYSTEM CONTROL REGISTER MAP
NVM REGISTER MAP
TRAPR
TRISG15
ODCG15
Bit 15
LATG15
Bit 15
Bit 15
ROI
RG15
—
—
—
WR
—
IOPUWR
Bit 14
TRISG14
ODCG14
WREN
Bit 14
LATG14
Bit 14
—
—
RG14
—
COSC<2:0>
DOZE<2:0>
Bit 13
WRERR
Bit 13
—
—
—
TRISG13
ODCG13
LATG13
Bit 13
—
RG13
Bit 12
Bit 12
—
—
—
(1)
TRISG12
ODCG12
—
—
LATG12
Bit 12
RG12
DOZEN
Bit 11
—
—
—
—
Bit 11
—
—
Bit 11
—
—
—
—
Bit 10
—
—
—
Bit 10
Bit 10
—
—
—
—
—
—
FRCDIV<2:0>
NOSC<2:0>
Bit 9
—
—
—
TRISG9
ODCG9
Bit 9
LATG9
Bit 9
RG9
—
—
VREGS
Bit 8
—
TRISG8
ODCG8
LATG8
Bit 8
Bit 8
RG8
—
—
CLKLOCK
EXTR
Bit 7
PLLPOST<1:0>
—
TRISG7
ODCG7
LATG7
Bit 7
Bit 7
RG7
—
Bit 6
SWR
TRISG6
ODCG6
LATG6
—
—
ERASE
Bit 6
RG6
Bit 6
SWDTEN
LOCK
Bit 5
—
Bit 5
Bit 5
—
—
—
—
—
PLLDIV<8:0>
WDTO
Bit 4
Bit 4
—
—
—
—
—
Bit 4
NVMKEY<7:0>
—
SLEEP
TRISG3
ODCG3
Bit 3
LATG3
Bit 3
CF
RG3
Bit 3
TUN<5:0>
PLLPRE<4::0>
TRISG2
ODCG2
Bit 2
IDLE
LATG2
Bit 2
RG2
—
Bit 2
NVMOP<3:0>
LPOSCEN
TRISG1
ODCG1
LATG1
Bit 1
Bit 1
BOR
RG1
Bit 1
TRISG0
ODCG0
LATG0
OSWEN
Bit 0
RG0
Bit 0
POR
Bit 0
Resets
Resets
F3CF
xxxx
xxxx
xxxx
xxxx
0300
0040
0030
0000
Resets
0000
0000
All
All
All
(1)
(2)
(1)