DSPIC33FJ64MC508 Microchip Technology Inc., DSPIC33FJ64MC508 Datasheet - Page 160

• Manufacturer Part Number: DSPIC33FJ64MC508
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJXXXMCX06/X08/X10 MOTOR CONTROL FAMILY
13.1
REGISTER 13-1:
DS70287A-page 158
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
ICTMR
R/W-0
U-0
—
Input Capture Registers
(1)
Timer selections may vary. Refer to the device data sheet for details.
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Module Stop in Idle Control bit
1 = Input capture module will halt in CPU Idle mode
0 = Input capture module will continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
ICTMR: Input Capture Timer Select bits
1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
ICI<1:0>: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
ICBNE: Input Capture Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
ICM<2:0>: Input Capture Mode Select bits
111 =Input capture functions as interrupt pin only when device is in Sleep or Idle mode
110 =Unused (module disabled)
101 =Capture mode, every 16th rising edge
100 =Capture mode, every 4th rising edge
011 =Capture mode, every rising edge
010 =Capture mode, every falling edge
001 =Capture mode, every edge (rising and falling)
000 =Input capture module turned off
R/W-0
U-0
—
ICxCON: INPUT CAPTURE x CONTROL REGISTER
(Rising edge detect only, all other control bits are not applicable.)
(ICI<1:0> bits do not control interrupt generation for this mode.)
ICI<1:0>
W = Writable bit
‘1’ = Bit is set
ICSIDL
R/W-0
R/W-0
R-0, HC
ICOV
U-0
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0, HC
ICBNE
U-0
—
R/W-0
U-0
—
© 2007 Microchip Technology Inc.
x = Bit is unknown
ICM<2:0>
R/W-0
U-0
—
R/W-0
U-0
—
bit 8
bit 0