HT46RU22 Holtek Semiconductor Inc., HT46RU22 Datasheet - Page 18

• Manufacturer Part Number: HT46RU22
• Description: Ht46ru22 -- A/d Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

The I/O functions of PA3 are shown below.
Note:
The PA5 and PA4 are pin-shared with INT and TMR pins
respectively.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0. If the PWM function is en-
abled, the PWM signal will appear on PD0 (if PD0 is op-
erating in output mode). Writing 1 to PD0 data register
will enable the PWM output function and writing 0 will
force the PD0 to remain at 0 . The I/O functions of PD0
is as shown.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
PWM
The microcontroller provides 1 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0. The PWM channel has its data registers denoted
as PWM(1AH). The frequency source of the PWM coun-
ter comes from f
ter. The waveforms of PWM outputs are as shown.
Once the PD0 is selected as the PWM outputs and the
output function of PD0 is enabled (PDC.0= 0 ), writing 1
to PD0 data register will enable the PWM output func-
tion and writing 0 will force the PD0 to stay at 0 .
A (6+2) bits mode PWM cycle is divided into four modu-
lation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
Rev. 1.20
Mode
PD0
I/O
Mode
PA3
I/O
The PFD frequency is the timer/event counter
overflowfrequencydivided by 2.
(Normal)
Logical
Input
(Normal)
I/P
Logical
Input
I/P
SYS
. The PWM registers is a 8-bit regis-
(Normal)
Logical
Output
(Normal)
O/P
Logical
Output
O/P
(PWM)
Logical
Input
Logical
(PFD)
I/P
Input
I/P
(Timer on)
(PWM)
PWM
(PFD)
O/P
PFD
O/P
18
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2. The group 2 is denoted by AC which is
the value of PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle 0 ~ modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1. The group 2 is denoted by AC which is
the value of PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
f
f
SYS
SYS
Modulation Frequency
Modulation cycle i
Modulation cycle i
/64 for (6+2) bits mode
/128 for (7+1) bits mode
Parameter
Parameter
(i=0~3)
(i=0~1)
PWM
AC (0~3)
AC (0~1)
PWM Cycle
i<AC
i AC
i<AC
i AC
Frequency
f
SYS
/256
HT46RU22
March 23, 2007
Duty Cycle
Duty Cycle
PWM Cycle
[PWM]/256
DC + 1
DC + 1
128
128
DC
DC
Duty
64
64