HT46RU22 Holtek Semiconductor Inc., HT46RU22 Datasheet
HT46RU22
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HT46RU22 Summary of contents
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... Supports PFD for sound generation HALT function and wake-up feature reduce power consumption General Description The HT46RU22 are 8-bit, high performance, RISC ar- chitecture microcontroller devices specifically designed for A/D applications that interface directly to analog sig- nals, such as those from sensors. The advantages of low power consumption, I/O flexibil- ...
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... Block Diagram Pin Assignment Rev. 1.20 2 HT46RU22 March 23, 2007 ...
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... Schmitt trigger reset input. Active low. Negative power supply, ground. Positive power supply TEST mode input pin It disconnects in normal operation +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH 3 HT46RU22 March 23, 2007 ...
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... =0. =0. =0. ¾ ¾ ¾ ¾ 0 ¾ ¾ ¾ ¾ 3V ¾ ¾ HT46RU22 Ta=25°C Typ. Max. Unit ¾ 5.5 V ¾ 5.5 V 0.6 1 0.8 1 ¾ ¾ ...
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... SYS SYS Rev. 1.20 Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 0 3.3V~5. Wake-up from HALT 0. Connect to external 64 pull-high resistor 2k 5 HT46RU22 Ta=25 C Typ. Max. Unit 4000 kHz 8000 kHz 4000 kHz 8000 kHz 90 180 s 65 130 s s 1024 *t SYS ...
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... Program Counter + Program Counter S10~S0: Stack register bits @7~@0: PCL bits 6 HT46RU22 * ...
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... These areas may function as normal program memory depending upon the requirements. Program Memory Table Location * Table Location P10~P8: Current program counter bits 7 HT46RU22 * March 23, 2007 ...
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... Rev. 1.20 Accumulator The accumulator is closely related to ALU operations also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. RAM Mapping 8 HT46RU22 March 23, 2007 ...
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... Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. Function Status (0AH) Register 9 HT46RU22 March 23, 2007 ...
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... To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to en- able an interrupt service, but RET will not. Function INTC0 (0BH) Register Function C Bus interrupt (1=enabled; 0=disabled) INTC1 (1EH) Register 10 HT46RU22 2 C Bus March 23, 2007 ...
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... Once an internal WDT oscillator (RC oscillator with pe- riod normally) is selected divided (by option to get the WDT time-out period). The minimum period of WDT time-out period is about 300ms~600ms. This time-out period may vary with tem- Watchdog Timer 11 HT46RU22 March 23, 2007 ...
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... If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. 12 HT46RU22 (sys- SYS March 23, 2007 ...
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... Timer/Event Counter Off Input/Output ports Input mode Stack Pointer Points to the top of the stack Rev. 1.20 Reset Circuit Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Timing Chart Reset Configuration 13 HT46RU22 March 23, 2007 ...
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... HT46RU22 RES Reset WDT Time-out (HALT) (HALT)* xxxx xxxx uuuu uuuu 00-0 1000 uu-u uuuu 000H 000H -uuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu ...
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... The overflow of the timer/event counter is one of the wake-up sources. No matter what the opera- tion mode is, writing ETI can disable the interrupt service. Function =f SYS =f /2 SYS =f /4 SYS =f /8 SYS =f /16 SYS =f /32 SYS =f /64 SYS =f /128 SYS TMRC (0EH) Register 15 HT46RU22 March 23, 2007 ...
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... Once the PFD option is se- lected, the PFD output signal is controlled by PA3 data register only. Writing 1 to PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain HT46RU22 March 23, 2007 ...
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... Rev. 1.20 Input/Output Ports PC0/TX Input/Output Ports PC1/RX Input/Output Ports 17 HT46RU22 March 23, 2007 ...
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... The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency f /64 for (6+2) bits mode SYS f /128 for (7+1) bits mode SYS 18 HT46RU22 AC (0~3) Duty Cycle i< (0~1) Duty Cycle i<AC 128 ...
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... ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and fall- ing edge means that the A/D conversion has started. In order to ensure the A/D conversion is completed, the START should remain at 0 until the EOCB is cleared to 0 (end of A/D conversion). 19 HT46RU22 March 23, 2007 ...
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... AN4 AN3 PB6 AN5 AN4 AN3 AN6 AN5 AN4 AN3 Port B Configuration ACS0 Analog Input Channel Selection 20 HT46RU22 PB2 PB1 PB0 PB2 PB1 AN0 PB2 AN1 AN0 AN2 AN1 AN0 AN2 AN1 AN0 AN2 AN1 AN0 ...
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... As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles Rev. 1.20 Bit5 Bit4 Bit3 ADRL (24H), ADRH (25H) Register /8 as the A/D clock SYS /8 as the A/D clock SYS 21 HT46RU22 Bit2 Bit1 Bit0 March 23, 2007 ...
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... START set START ; reset A/D clr START ; start A EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.20 A/D Conversion Timing 22 HT46RU22 March 23, 2007 ...
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... I C Bus at the 9th clock. If the re- ceiver wants to continue to receive the next data, this bit must be reset to 0 before receiving data. Low Voltage Reset 23 HT46RU22 2 C Bus Bus as a transmitter or 2 ...
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... Unused bit, read as 0 RXAK is cleared to 0 when the master receives an 8-bit data and acknowledg- 0 RXAK ment at the 9th clock, RXAK is set to 1 means not acknowledged. HSR (22H) Register 24 HT46RU22 2 C Bus, the Function 2 C Bus function C Bus interrupt. Function 2 C Bus inter- ...
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... Rev. 1.20 25 HT46RU22 March 23, 2007 ...
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... The SRW is cleared to 0 means that the master wants to write 2 data to the I C Bus, so the slave device must read data 2 from the I C Bus as a receiver. 26 HT46RU22 2 C Bus. The slave device 2 C Bus, so the slave de- March 23, 2007 ...
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... The transmitter checks the acknowledge bit (RXAK) to continue to write data to the I change to receive mode and dummy read the HDR reg- ister to release the SDA line and the master sends the STOP signal. 27 HT46RU22 2 C Bus. The 2 C Bus or March 23, 2007 ...
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... UART Bus Serial Interface The HT46RU22 devices contain an integrated full-du- plex asynchronous serial communications UART inter- face that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data seri- ally by transferring a frame of data with eight or nine ...
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... The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of an overrun. The NF flag can be cleared by a software sequence which will involve a read to the USR status register, followed by an ac- cess to the RXR data register. 29 HT46RU22 March 23, 2007 ...
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... UCR1, UCR2, and BRG registers will re- main unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled it will restart in the same configuration. 30 HT46RU22 March 23, 2007 ...
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... UARTEN bit is equal to 1 the RX pin will be controlled by the UART. Clearing the RXEN bit during a transmission will cause the data reception to be aborted and will reset the receiver. If this oc- curs, the RX pin can be used as a general purpose I/O pin. 31 HT46RU22 March 23, 2007 ...
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... Baud Rates for BRGH=0 f =7.159MHz f =4MHz SYS SYS Kbaud Error BRG Kbaud 207 0.300 1.203 0.23 51 1.202 2.38 -0.83 25 2.404 4.863 1.32 12 4.808 9.322 -2.9 6 8.929 18.64 -2.9 2 20.83 37.29 -2.9 1 55.93 -2.9 0 62.5 111.86 -2.9 32 HT46RU22 f SYS 1 (BRx64) 8000000 1 12.0208 x ( 9600 64 ) 9615 f =3.579545MHz SYS Error BRG Kbaud Error 0.00 185 0.300 0.00 0.16 46 1.19 -0.83 0.16 22 2.432 1.32 0.16 11 4.661 -2.9 -6.99 5 9.321 -2.9 8.51 2 18.643 -2 ...
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... The fol- lowing table shows various formats for data trans- mission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. 33 HT46RU22 f =3.579545MHz SYS Error BRG Kbaud Error 0 ...
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... TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. 34 HT46RU22 March 23, 2007 ...
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... USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver idle condition. 35 HT46RU22 March 23, 2007 ...
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... UART interrupt vector where it can be serviced before returning to the main program. Four of these conditions, have a corre- sponding USR register flag, which will generate a UART interrupt if its associated interrupt enable flag in UART Interrupt Scheme 36 HT46RU22 March 23, 2007 ...
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... Note also that as it takes 1024 sys- tem clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. 37 HT46RU22 UART Interrupt Generated X March 23, 2007 ...
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... PD0: Level output or PWM output WDT time-out period selection Low voltage reset selection: Enable or disable LVR function Bus function: Enable or disable Rev. 1.20 Options HT46RU22 March 23, 2007 ...
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... RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.20 C1 0pF 10k 10pF 12k 0pF 10k 25pF 10k 25pF 10k 35pF 27k 300pF 9.1k 300pF 10k 300pF 10k 39 HT46RU22 March 23, 2007 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.20 Description 40 HT46RU22 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.20 Description 41 HT46RU22 Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.20 PDF PDF PDF PDF PDF HT46RU22 March 23, 2007 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.20 PDF PDF PDF addr PDF PDF HT46RU22 March 23, 2007 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.20 PDF PDF PDF PDF PDF HT46RU22 March 23, 2007 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.20 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT46RU22 March 23, 2007 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.20 Program Counter+1 PDF PDF PDF addr PDF PDF HT46RU22 March 23, 2007 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.20 PDF PDF Program Counter+1 PDF PDF PDF PDF HT46RU22 March 23, 2007 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.20 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT46RU22 March 23, 2007 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.20 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT46RU22 March 23, 2007 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.20 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT46RU22 March 23, 2007 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.20 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT46RU22 March 23, 2007 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.20 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT46RU22 March 23, 2007 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.20 PDF PDF PDF PDF PDF HT46RU22 March 23, 2007 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.20 PDF PDF PDF HT46RU22 March 23, 2007 ...
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... Package Information 24-pin SKDIP (300mil) Outline Dimensions Symbol Rev. 1.20 Dimensions in mil Min. Nom. 1235 255 125 125 16 50 100 295 345 0 55 HT46RU22 Max. 1265 265 135 145 20 70 315 360 15 March 23, 2007 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.20 Dimensions in mil Min. Nom. 394 290 14 590 HT46RU22 Max. 419 300 20 614 104 March 23, 2007 ...
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... SSOP (150mil) Outline Dimensions Symbol Rev. 1.20 Dimensions in mil Min. Nom. 228 150 8 335 HT46RU22 Max. 244 157 12 346 March 23, 2007 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 24S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.20 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 16.8+0.3 0.2 22.2 0.2 58 HT46RU22 March 23, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.20 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.55+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.9 0.1 15.9 0.1 3.1 0.1 0.35 0.05 21.3 Dimensions in mm 16.0+0.3 0.1 8.0 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 6.5 0.1 9.5 0.1 2.1 0.1 0.3 0.05 13.3 59 HT46RU22 March 23, 2007 ...
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... Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 60 HT46RU22 March 23, 2007 ...