HT46RU22 Holtek Semiconductor Inc., HT46RU22 Datasheet - Page 15

• Manufacturer Part Number: HT46RU22
• Description: Ht46ru22 -- A/d Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an 8-bit
programmable count-up counter and the clock may come
from an external source or the system clock.
Using the internal system clock, there is only one refer-
ence time-base. The internal clock source comes from
f
external events, measure time internals or pulse widths,
or generate an accurate time base. While using the in-
ternal clock allows the user to generate an accurate time
base.
There are two registers related to the timer/event coun-
ter; TMR ([0DH]), TMRC ([0EH]). Two physical registers
are mapped to TMR location; writing TMR makes the
starting value be placed in the timer/event counter
preload register and reading TMR gets the contents of
the timer/event counter. The TMRC is a timer/event
counter control register, which defines some options.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the f
pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR). The
counting is based on the f
Rev. 1.20
SYS
. Using external clock input allows the user to count
Bit No.
0
1
2
3
4
5
6
7
Label
PSC0
PSC1
PSC2
TON
TM0
TM1
TE
INT
.
To define the prescaler stages, PSC2, PSC1, PSC0=
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
To enable or disable timer counting
(0=disabled; 1=enabled)
Unused bit, read as 0
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
INT
INT
INT
INT
INT
INT
INT
INT
INT
=f
=f
=f
=f
=f
=f
=f
=f
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
clock. The
TMRC (0EH) Register
/2
/4
/8
/16
/32
/64
/128
15
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once over-
flow occurs, the counter is reloaded from the timer/event
counter preload register and generates the interrupt re-
quest flag (TF; bit 5 of INTC0) at the same time.
In the pulse width measurement mode with the TON and
TE bits equal to 1, once the TMR has received a tran-
sient from low to high (or high to low if the TE bits is 0 )
it will start counting until the TMR returns to the original
level and resets the TON. The measured result will re-
main in the timer/event counter even if the activated
transient occurs again. In other words, only 1 cycle mea-
surement can be done. Until setting the TON, the cycle
measurement will function again as long as it receives
further transient pulse. Note that, in this operating mode,
the timer/event counter starts counting not according to
the logic level but according to the transient edges. In
the case of counter overflows, the counter is reloaded
from the timer/event counter preload register and issues
the interrupt request just like the other two modes. To
enable the counting operation, the timer ON bit (TON;
bit 4 of TMRC) should be set to 1. In the pulse width
measurement mode, the TON will be cleared automati-
cally after the measurement cycle is completed. But in
the other two modes the TON can only be reset by in-
structions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the opera-
tion mode is, writing a 0 to ETI can disable the interrupt
service.
Function
HT46RU22
March 23, 2007