HT46RU22 Holtek Semiconductor Inc., HT46RU22 Datasheet - Page 10

• Manufacturer Part Number: HT46RU22
• Description: Ht46ru22 -- A/d Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
4 of INTC0) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC0), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC0),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a sub-
routine call to location 0CH will occur. The related inter-
rupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
Rev. 1.20
2~3, 6~7
Bit No.
Bit No.
0
1
2
3
4
5
6
7
0
1
4
5
Label
Label
EADI
EURI
ADF
URF
EMI
EEI
ETI
EIF
EHI
HIF
TF
Controls the master (global) interrupt (1= enabled; 0= disabled)
Controls the external interrupt (1= enabled; 0= disabled)
Controls the timer/event counter interrupt (1= enabled; 0= disabled)
Controls the A/D converter interrupt (1= enabled; 0= disabled)
External interrupt request flag (1= active; 0= inactive)
Internal timer/event counter request flag (1= active; 0= inactive)
A/D converter request flag (1= active; 0= inactive)
For test mode used only.
Must be written as 0 ; otherwise may result in unpredictable operation.
Controls the I
Control the UART interrupt ( 1=enable ; 0=disable )
Unused bit, read as 0
I
UART request flag ( 1=active; 0:inactive )
2
C Bus interrupt request flag (1=active; 0=inactive)
2
C Bus interrupt (1=enabled; 0=disabled)
INTC0 (0BH) Register
INTC1 (1EH) Register
10
The I
interrupt request flag (HIF; bit 4 of INTC1), caused by a
slave address match (HAAS= 1 ) or 1 byte of data
transfer is completed. When the interrupt is enabled, the
stack is not full and the HIF bit is set, a subroutine call to lo-
cation 10H will occur. The related interrupt request flag
(HIF) will be reset and the EMI bit cleared to disable further
interrupts.
The UART interrupt is initialized by setting the UART in-
terrupt request flag (URF; bit 7 of INTC1), caused by
UART transmission/reception completion or address de-
tection. When the interrupt is enabled, the stack is not full
and the URF bit is set, a subroutine call to location 014H
will occur. The related interrupt request flag (URF) will be
reset and the EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, RET or
able an interrupt service, but RET will not.
RETI may be invoked. RETI will set the EMI bit to en-
Function
Function
2
C Bus interrupt is initialized by setting the I
HT46RU22
March 23, 2007
2
C Bus