FIN24C Fairchild Semiconductor, FIN24C Datasheet - Page 17

• Manufacturer Part Number: FIN24C
• Description: Serdes Low Voltage 24-bit Bi-directional Serializer/deserializer
• Manufacturer: Fairchild Semiconductor

©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
Notes:
4. Typical Values are given for V
5. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
6. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
7. Signals are transmitted from the serializer source synchronously. In some cases, data is transmitted when the clock
8. Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP
Control Logic Timing Controls
Note:
9. Deserializer enable time includes the amount of time required for internal voltage and current references to stabilize.
Capacitance
t
t
t
t
t
t
Symbol
t
t
PLZ
PZL
PLZ
PZL
PLZ
PZL
PHL_DIR
Symbol
PLH_DIR
device and negative values refer to current flowing out of pins. Voltage is referenced to GROUND unless otherwise
specified (except ΔV
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies based
on the operating mode of the device.
remains at a high state. Skew should only be measured when data and clock are transitioning at the same time. Total
measured input skew is a combination of output skew from the serializer, load variations, and ISI and jitter effects.
occurs approximately eight bit times after a data transition or six bit times after the first falling edge of CSKO. Variation
of the data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP path
and propagation delay differences on the various data pins. If the CKREF is not equal to STROBE for the serializer,
the CKP signal does not maintain a 50% duty cycle. The low time of the CKP remains 13 bit times.
This time is significantly less than the PLL lock time and does not impact overall system startup time.
C
IO-DIFF
C
, t
, t
, t
, t
, t
, t
C
IN
IO
PHZ
PZH
PHZ
PZH
PHZ
PZH
,
Propagation Delay
DIRI-to-DIRO
Propagation Delay
DIRI-to-DP
Propagation Delay
DIRI-to-DP
Deserializer Disable Time:
S0 or S1 to DP
Deserializer Enable Time:
S0 or S1 to DP
Serializer Disable Time:
S0 or S1 to CKSO, DS
Serializer Enable Time:
S0 or S1 to CKSO, DS
Capacitance of Input Only Signals,
CKREF, STROBE, S1, S2, DIRI
Capacitance of Parallel Port Pins
DP[1:12]
Capacitance of Differential I/O Signals
Parameter
OD
and V
Parameter
OD
DD
).
= 2.775V and T
DIRI LOW-to-HIGH or HIGH-to-LOW
DIRI LOW-to-HIGH
DIRI HIGH-to-LOW
DIRI = 0,
S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 30
DIRI = 0,
S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 30
DIRI = 1,
S1(2) = 0 and S2(1) = HIGH-to-LOW, Figure 28
DIRI = 1,
S1(2) and S2(1) = LOW-to-HIGH, Figure 28
(10)
A
= 25°C. Positive current values refer to the current flowing into
Test Conditions
DIRI = 1, S1 = S2 = 0,
V
DIRI = 1, S1 = S2 = 0,
V
DIRI = 0, S1 = S2 = 0,
V
17
DDP
DDP
DDP
Test Conditions
= 2.5V
= 2.5V
= 2.775V
Min.
Min. Typ. Max. Units
Typ. Max. Units
2.0
2.0
2.0
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17.0
25.0
25.0
25.0
25.0
65.0
2.0
pF
pF
pF
µs
ns
ns
ns
ns
ns
ns