XA-SCC NXP Semiconductors, XA-SCC Datasheet - Page 35

• Manufacturer Part Number: XA-SCC
• Description: Cmos 16-bit Communications Microcontroller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1999 Feb 23
CMOS 16-bit communications microcontroller
CAS (BHE/BLE)
On all cycles on 8 bit bus, BHE remains high (inactive).
WARNING: On the external bus, ALL XA–SCC reads are 16 bit Reads. If the CPU instruction only specifies 8 bits, then the CPU uses the appropriate byte, and discards the extra
byte. Thus “8 Bit Reads” and “16 bit Reads” appear to be identical on the bus. On an 8 bit bus, this will appear as two consecutive 8 bit reads even though the CPU will only use one
of the two bytes.
WARNING: Some 8 bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and least expensive) solution is to
operate these 8 bit devices on a 16 bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this technique is that byte reads are faster
than on an 8 bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
CLKOUT
RAS (CS)
CLKOUT
A19–A1
D7–D0
BLE
CS
OE
A0
WE
NOTE: If only one byte is being written, then only the corresponding CAS signal goes active. On 8 bit bus, CASH is inactive, and CASL goes active for
D
A
É É É É É
É É É É É
DRIVEN BY XA
: OE is inactive during all writes.
both even and odd addressed bytes.
t
CHAV
t
CHAV
t
CHDV
t
t
AVSL
AVSL
Figure 16. Generic (SRAM, Flash, I/O Device, etc.) Read (16 Bit or 8 Bit) on 8 Bit Bus
RAS ADDRESS
EVEN BYTE ADDRESS
t
CHSL
Figure 15. DRAM Write (on 16 Bit Bus, also 8 Bit Write on 8 Bit Bus)
t
CHSL
NOTE 3
t
CHAH
t
DIS
t
CHSL
VALID DATA
t
AVSL
NOTE 2
t
ODD BYTE ADDRESS
CHAV
NOTE 1
35
CAS ADDRESS
t
DIS
NOTE 2
t
DIH
t
t
CHSH
AHDR
t
OHDE
t
CHSH
DRIVEN
BY XA
t
CHAH
t
CHSH
Preliminary specification
XA-SCC
SU01136
SU01137