XA-SCC NXP Semiconductors, XA-SCC Datasheet - Page 10

• Manufacturer Part Number: XA-SCC
• Description: Cmos 16-bit Communications Microcontroller
• Manufacturer: NXP Semiconductors

*
# SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-SCC.
1. The XA-SCC implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be
2. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
3. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt
4. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh
5. SFR is loaded from the reset vector.
6. F1, F0, and P reset to 0. All other bits are loaded from the reset vector.
7. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to 1, the others will be 0. RSTSRC[7] enables the ResetOut
8. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.
Philips Semiconductors
NOTES:
1999 Feb 23
SWE
SWR*
TCON*
TH0
TH1
TL0
TL1
TMOD
TSTAT*
WDCON*
WDL
WFEED1
WFEED2
CMOS 16-bit communications microcontroller
NAME
SFRs marked with an asterisk (*) are bit addressable.
8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data
in the upper byte.
purposes in future XA derivatives. The reset value shown for these bits is 0.
or other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a
read-modify-write operation. XA-SCC SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in
WDCON).
and PnCFGB register will contain 00h. See warning in XA-SCC User Manual about P3.2_Timer0_ResetOut pin during first 258 clocks after
power up. Basically, during this period, this pin may output a strongly driven low pulse. If the pulse does occur, it will terminate in a
transition to high at a time no later than the 259th system clock after valid VCC power up.
function; 1 = Enabled, 0 = Disabled. See XA-SCC User Manual for details; RSTSRC[7] differs in function from most other XA derivatives.
Software Interrupt Enable
Software Interrupt Request
Timer 0/1 Control
Timer 0 High
Timer 1 High
Timer 0 Low
Timer 1 Low
Timer 0/1 Mode
Timer 0/1 Extended Status
Watchdog Control
Watchdog Timer Reload
Watchdog Feed 1
Watchdog Feed 2
DESCRIPTION
Address
47Ah
42Ah
45Ch
45Dh
45Eh
410h
451h
453h
450h
452h
411h
41Fh
45Fh
SFR
GATE
PRE2
TF1
2FF
357
287
28F
–
–
–
MSB
SWR7
SWE7
PRE1
TR1
28E
2FE
356
286
C/T
–
10
SWR6
SWE6
PRE0
TF0
28D
2FD
355
285
M1
–
BIT FUNCTIONS AND ADDRESSES
SWR5
SWE5
TR0
28C
2FC
354
284
M0
–
–
SWR4
SWE4
GATE
28B
2FB
353
283
IE1
–
–
WDRUN
SWR3
SWE3
T1OE
28A
2FA
352
282
C/T
IT1
WDTOF
SWE2
SWR2
351
281
289
2F9
IE0
M1
–
Preliminary specification
LSB
XA-SCC
SWE1
SWR1
T0OE
350
280
288
2F8
IT0
M0
–
RESET
VALUE
Note 8
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
xx
xx