IDT72V2113 Integrated Device Technology, IDT72V2113 Datasheet - Page 7

• Manufacturer Part Number: IDT72V2113
• Description: 256k X 18 / 512k X 9 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTE:
1. Inputs should not change state after Master Reset.
PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES)
PIN DESCRIPTION (BGA PACKAGE ONLY)
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 41-45 and Figures 31-33.
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
ASYR
ASYW
TCK
TDI
TDO
TMS
TRST
RM
RT
SEN
WCLK/
WR
WEN
V
Symbol
Symbol
CC
(2)
(1)
(2)
(2)
(2)
(2)
(1)
(1)
Retransmit Timing
Mode
Retransmit
Serial Enable
Write Clock/
Write Strobe
Write Enable
+3.3V Supply
Asynchronous
Read Port
Asynchronous
Write Port
JTAG Clock
JTAG Test Data
Input
JTAG Test Data
Output
JTAG Mode
JTAG Reset
Name
Name
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
normal latency mode.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings. RT is useful to reread data from the first physical location of the FIFO.
SEN enables serial loading of programmable flag offsets.
If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the
FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Asynchronous operation
of the WCLK/WR input is only available in the BGA package.
WEN enables WCLK for writing data into the FIFO memory and offset registers.
These are V
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
will select Asynchronous operation.
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the
device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register.
An internal pull-up resistor forces TDI HIGH if left unconnected.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through
its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller will automatically reset upon
power-up. If the JTAG function is not used then this signal should to be tied to GND.
CC
supply inputs and must be connected to the 3.3V supply rail.
TM
NARROW BUS FIFO
TM
7
NARROW BUS FIFO
Description
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
APRIL 6, 2006