IDT72V2113 Integrated Device Technology, IDT72V2113 Datasheet - Page 32

• Manufacturer Part Number: IDT72V2113
• Description: 256k X 18 / 512k X 9 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR), will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
3. OE = LOW
4. W
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
WCLK
NOTES:
1. x9 to x9 mode: X = 17 for the IDT72V2103 and X = 18 for the IDT72V2113.
2. All other modes: X = 16 for the IDT72V2103 and X = 17 for the IDT72V2113.
Q
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
WCLK
RCLK
0
SEN
WEN
REN
- Q
PAE
PAF
LD
1
SI
OR
, W
HF
RT
If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113.
If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
BIT 0
t
t
ENS
LDS
t
DS
t
ENS
t
W
RTS
x+1
t
t
LDH
ENH
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
1
t
A
EMPTY OFFSET
t
t
ENH
HF
t
SKEW2
1
W
TM
1
NARROW BUS FIFO
2
t
PAFS
2
t
A
TM
BIT X
NARROW BUS FIFO
32
(1)
W
2
BIT 0
(3)
3
t
A
t
PAES
FULL OFFSET
W
3
(3)
t
4
A
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BIT X
W
t
t
4
t
ENH
LDH
DH
(3)
(1)
APRIL 6, 2006
5
t
A
t
ENH
6119 drw18
6119 drw17
W
5