IDT72V2113 Integrated Device Technology, IDT72V2113 Datasheet - Page 6

• Manufacturer Part Number: IDT72V2113
• Description: 256k X 18 / 512k X 9 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTE:
1. Inputs should not change state after Master Reset.
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
PIN DESCRIPTION (TQFP & BGA PACKAGES)
RD
Symbol
BE
D
EF/OR
FF/IR
FSEL0
FSEL1
FWFT/SI First Word Fall
HF
IP
IW
LD
MRS
OE
OW
PAE
PAF
PFM
PRS
Q
REN
RCLK/
0
0
(1)
–D
(1)
–Q
(1)
(1)
(1)
17
17
(1)
(1)
*Big-Endian/
Little-Endian
Data Inputs
Empty Flag/
Output Ready
Full Flag/
Input Ready
Flag Select Bit 0
Flag Select Bit 1
Through/Serial In
Half-Full Flag
Interspersed Parity
Input Width
Load
Master Reset
Output Enable
Output Width
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Programmable
Flag Mode
Partial Reset
Data Outputs
Read Enable
Read Clock/
Read Strobe
Name
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will
select Little-Endian format.
Data inputs for a 18- or 9-bit bus. When in 18-bit mode, D
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. In
FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the
FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO
memory.
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions
as a serial input for loading offset registers.
HF indicates whether the FIFO memory is more or less than half-full.
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
Parity mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It
does not effect the data written to and read from the FIFO.
This pin selects the bus width of the write port. During Master Reset, when IW is LOW, the write port will be
configured with a x18 bus width. If IW is HIGH, the write port will be a x9 bus width.
This is a dual purpose pin. During Master Reset, the state of the LD input, along with FSEL0 and FSEL1, determines
one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offset registers.
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the
FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable
flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency
timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
This pin selects the bus width of the read port. During Master Reset, when OW is LOW, the read port willbe config-
ured with a x18 bus width. If OW is HIGH, the read port will be a x9 bus width.
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
will select Synchronous Programmable flag timing mode.
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are
all retained.
Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q
used, and the unused outputs, Q
state of OE.
REN enables RCLK for reading data from the FIFO memory and offset registers.
If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
Asynchronous operation of the RCLK/RD input is only available in the BGA package.
OE controls the output impedance of Q
and the unused inputs, D
programmable flags PAE and PAF. There are up to eight possible settings available.
TM
NARROW BUS FIFO
9
–D
17,
TM
9
should be tied LOW.
-Q
NARROW BUS FIFO
6
17
should not be connected. Outputs are not 5V tolerant regardless of the
n.
Description
0
–D
0
–Q
17
17
are used. When in 9-bit mode, D
are used and when in 9-bit mode, Q
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
APRIL 6, 2006
0
–D
8
0
are used
–Q
8
are